/********************************************************************
 * Copyright (C) 2013-2014 Texas Instruments Incorporated.
 * 
 *  Redistribution and use in source and binary forms, with or without 
 *  modification, are permitted provided that the following conditions 
 *  are met:
 *
 *    Redistributions of source code must retain the above copyright 
 *    notice, this list of conditions and the following disclaimer.
 *
 *    Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the 
 *    documentation and/or other materials provided with the   
 *    distribution.
 *
 *    Neither the name of Texas Instruments Incorporated nor the names of
 *    its contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
 *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
 *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
 *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
 *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
 *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
*/
#ifndef CSLR_PCIEPHYRX_H_
#define CSLR_PCIEPHYRX_H_

#ifdef __cplusplus
extern "C"
{
#endif
#include <ti/csl/cslr.h>
#include <ti/csl/tistdtypes.h>


/**************************************************************************
* Register Overlay Structure for __ALL__
**************************************************************************/
typedef struct {
    volatile Uint32 INPUT_ENS_REG1;
    volatile Uint32 INPUT_ENS_REG2;
    volatile Uint32 LDO_CTRL_REG1;
    volatile Uint32 ANA_PROGRAMMABILITY_REG1;
    volatile Uint32 TRIM_REG1;
    volatile Uint32 TRIM_REG2;
    volatile Uint32 TRIM_REG3;
    volatile Uint32 TRIM_REG4;
    volatile Uint32 TRIM_OBSERVE_REG1;
    volatile Uint32 DLL_REG1;
    volatile Uint32 DIGITAL_MODES_REG1;
    volatile Uint32 SAMPLER_OFFSET_REG1;
    volatile Uint32 SAMPLER_OFFSET_REG2;
    volatile Uint32 SAMPLER_OFFSET_REG3;
    volatile Uint32 EQUALIZER_REG1;
    volatile Uint32 EQUALIZER_REG2;
    volatile Uint32 EYESCAN_REG1;
    volatile Uint32 IO_AND_A2D_OVERRIDES_REG1;
    volatile Uint32 IO_AND_A2D_OVERRIDES_REG2;
    volatile Uint32 TESTABILITY_CTRL_REG1;
    volatile Uint32 OBSERVE_REG1;
    volatile Uint32 OBSERVE_REG2;
    volatile Uint32 OBSERVE_REG3;
    volatile Uint32 DFT_OBSERVE_REG4;
    volatile Uint32 DFT_OBSERVE_REG5;
    volatile Uint32 DLLOFFSET_TRIM_REG;
} CSL_PCIEPHYRXRegs;


/**************************************************************************
* Register Macros
**************************************************************************/

/* Enable controls for different analog and digital circuits in the IP. */
#define CSL_PCIEPHYRX_INPUT_ENS_REG1                            (0x0U)

/* Enable controls for different analog and digital circuits in the IP. */
#define CSL_PCIEPHYRX_INPUT_ENS_REG2                            (0x4U)

/* Controls for LDO circuits. */
#define CSL_PCIEPHYRX_LDO_CTRL_REG1                             (0x8U)

/* Some programmability for different analog circuits in the IP. */
#define CSL_PCIEPHYRX_ANA_PROGRAMMABILITY_REG1                  (0xCU)

/* The IP requires some values to be remembered in EFUSE. This register 
 * provides an alternative to EFUSE. */
#define CSL_PCIEPHYRX_TRIM_REG1                                 (0x10U)

/* The IP requires some values to be remembered in EFUSE. This register 
 * provides an alternative to EFUSE. */
#define CSL_PCIEPHYRX_TRIM_REG2                                 (0x14U)

/* The IP requires some values to be remembered in EFUSE. This register 
 * provides an alternative to EFUSE. */
#define CSL_PCIEPHYRX_TRIM_REG3                                 (0x18U)

/* The IP requires some values to be remembered in EFUSE. This register 
 * provides an alternative to EFUSE. */
#define CSL_PCIEPHYRX_TRIM_REG4                                 (0x1CU)

/* The registers need to be read at the end of TRIM procedure. */
#define CSL_PCIEPHYRX_TRIM_OBSERVE_REG1                         (0x20U)

/* In the high speed reception mode, a delay locked loop is used for 
 * generating 4 equally spaced phases of the pll_clk (after the bypassing by 
 * MEM_en_pllbyp and the division by MEM_plldiv) for use by the phase 
 * interpolator (after the DCC). These register bits are related to trimming 
 * of that circuit. The default values of all the wait time related registers 
 * correspond to 10MHz auxck1. */
#define CSL_PCIEPHYRX_DLL_REG1                                  (0x24U)

/* This register contains control bits which affect different circuits in 
 * digital section of the IP. */
#define CSL_PCIEPHYRX_DIGITAL_MODES_REG1                        (0x28U)

/* In the high speed reception mode, the 4 data samplers in analog sample the 
 * input differential rxp/rxn at 4 equally spaced phases of the pll_clk (after 
 * the bypassing by MEM_en_pllbyp and the division by MEM_plldiv and after the 
 * DCC and DLL etc.). The samples are processed depending on the MEM_hs_rate 
 * register and those final outputs are reffered to as ODD, OETR (odd to even 
 * transition data), EVEN and EOTR (even to odd transition data) samplers. The 
 * process dependent offset in these samplers is digitally compensated using a 
 * calibration circuit. */
#define CSL_PCIEPHYRX_SAMPLER_OFFSET_REG1                       (0x2CU)

/* This register is used in forcing the offset code of the 4 data sampler for 
 * testability. */
#define CSL_PCIEPHYRX_SAMPLER_OFFSET_REG2                       (0x30U)

/* This register is used in forcing the offset code of the 4 data sampler for 
 * testability and determining other Calibration algorithm related settings. */
#define CSL_PCIEPHYRX_SAMPLER_OFFSET_REG3                       (0x34U)

/* The IP has an Equalizer (with analog and digital parts) which addresses 
 * Inter Symbol Interference (ISI). This register is for its controllability. 
 * See Equalizer section for details. */
#define CSL_PCIEPHYRX_EQUALIZER_REG1                            (0x38U)

/* This register reads out the present status of the Equalizer level and zero 
 * location controls. */
#define CSL_PCIEPHYRX_EQUALIZER_REG2                            (0x3CU)

/* This register is used in the Eye Scan height and width measurement 
 * procedures. */
#define CSL_PCIEPHYRX_EYESCAN_REG1                              (0x40U)

/* This register has the override value and override controls for Input/Output 
 * pins and some Analog-Digital interface pins. This register should be left 
 * at their respective defaults by SoC users. These are to be used in test and 
 * debug of the IP. */
#define CSL_PCIEPHYRX_IO_AND_A2D_OVERRIDES_REG1                 (0x44U)

/* This register has the override value and override controls for Input/Output 
 * pins and some Analog-Digital interface pins. This register should be left 
 * at their respective defaults by SoC users. These are to be used in test and 
 * debug of the IP. */
#define CSL_PCIEPHYRX_IO_AND_A2D_OVERRIDES_REG2                 (0x48U)

/* This register has several Test mode related enables */
#define CSL_PCIEPHYRX_TESTABILITY_CTRL_REG1                     (0x4CU)

/* This register reflects the present state of some output pins and some 
 * internal registers. To be used for design observability. */
#define CSL_PCIEPHYRX_OBSERVE_REG1                              (0x50U)

/* This register reflects the present state of some internal registers. To be 
 * used for design observability. */
#define CSL_PCIEPHYRX_OBSERVE_REG2                              (0x54U)

/* This register reflects the present state of some internal nodes. To be used 
 * for design observability. */
#define CSL_PCIEPHYRX_OBSERVE_REG3                              (0x58U)

/* This register reflects the present state of some internal nodes. To be used 
 * for design observability. */
#define CSL_PCIEPHYRX_DFT_OBSERVE_REG4                          (0x5CU)

/* This register reflects the present state of some internal nodes. To be used 
 * for design observability. */
#define CSL_PCIEPHYRX_DFT_OBSERVE_REG5                          (0x60U)

/* The IP requires some values to be remembered in EFUSE. This register 
 * provides an alternative to EFUSE. */
#define CSL_PCIEPHYRX_DLLOFFSET_TRIM_REG                        (0x64U)


/**************************************************************************
* Field Definition Macros
**************************************************************************/

/* INPUT_ENS_REG1 */

#define CSL_PCIEPHYRX_INPUT_ENS_REG1_MEM_EN_RXA_MASK            (0x80000000U)
#define CSL_PCIEPHYRX_INPUT_ENS_REG1_MEM_EN_RXA_SHIFT           (31U)
#define CSL_PCIEPHYRX_INPUT_ENS_REG1_MEM_EN_RXA_RESETVAL        (0x00000000U)
#define CSL_PCIEPHYRX_INPUT_ENS_REG1_MEM_EN_RXA_MAX             (0x00000001U)

#define CSL_PCIEPHYRX_INPUT_ENS_REG1_MEM_OVRD_EN_RXA_MASK       (0x40000000U)
#define CSL_PCIEPHYRX_INPUT_ENS_REG1_MEM_OVRD_EN_RXA_SHIFT      (30U)
#define CSL_PCIEPHYRX_INPUT_ENS_REG1_MEM_OVRD_EN_RXA_RESETVAL   (0x00000000U)
#define CSL_PCIEPHYRX_INPUT_ENS_REG1_MEM_OVRD_EN_RXA_MAX        (0x00000001U)

#define CSL_PCIEPHYRX_INPUT_ENS_REG1_MEM_EN_BG_MASK             (0x20000000U)
#define CSL_PCIEPHYRX_INPUT_ENS_REG1_MEM_EN_BG_SHIFT            (29U)
#define CSL_PCIEPHYRX_INPUT_ENS_REG1_MEM_EN_BG_RESETVAL         (0x00000000U)
#define CSL_PCIEPHYRX_INPUT_ENS_REG1_MEM_EN_BG_MAX              (0x00000001U)

#define CSL_PCIEPHYRX_INPUT_ENS_REG1_MEM_OVRD_EN_BG_MASK        (0x10000000U)
#define CSL_PCIEPHYRX_INPUT_ENS_REG1_MEM_OVRD_EN_BG_SHIFT       (28U)
#define CSL_PCIEPHYRX_INPUT_ENS_REG1_MEM_OVRD_EN_BG_RESETVAL    (0x00000000U)
#define CSL_PCIEPHYRX_INPUT_ENS_REG1_MEM_OVRD_EN_BG_MAX         (0x00000001U)

#define CSL_PCIEPHYRX_INPUT_ENS_REG1_MEM_EN_RXALDO_MASK         (0x08000000U)
#define CSL_PCIEPHYRX_INPUT_ENS_REG1_MEM_EN_RXALDO_SHIFT        (27U)
#define CSL_PCIEPHYRX_INPUT_ENS_REG1_MEM_EN_RXALDO_RESETVAL     (0x00000000U)
#define CSL_PCIEPHYRX_INPUT_ENS_REG1_MEM_EN_RXALDO_MAX          (0x00000001U)

#define CSL_PCIEPHYRX_INPUT_ENS_REG1_MEM_OVRD_EN_RXALDO_MASK    (0x04000000U)
#define CSL_PCIEPHYRX_INPUT_ENS_REG1_MEM_OVRD_EN_RXALDO_SHIFT   (26U)
#define CSL_PCIEPHYRX_INPUT_ENS_REG1_MEM_OVRD_EN_RXALDO_RESETVAL  (0x00000000U)
#define CSL_PCIEPHYRX_INPUT_ENS_REG1_MEM_OVRD_EN_RXALDO_MAX     (0x00000001U)

#define CSL_PCIEPHYRX_INPUT_ENS_REG1_MEM_EN_RXDLDO_MASK         (0x02000000U)
#define CSL_PCIEPHYRX_INPUT_ENS_REG1_MEM_EN_RXDLDO_SHIFT        (25U)
#define CSL_PCIEPHYRX_INPUT_ENS_REG1_MEM_EN_RXDLDO_RESETVAL     (0x00000000U)
#define CSL_PCIEPHYRX_INPUT_ENS_REG1_MEM_EN_RXDLDO_MAX          (0x00000001U)

#define CSL_PCIEPHYRX_INPUT_ENS_REG1_MEM_OVRD_EN_RXDLDO_MASK    (0x01000000U)
#define CSL_PCIEPHYRX_INPUT_ENS_REG1_MEM_OVRD_EN_RXDLDO_SHIFT   (24U)
#define CSL_PCIEPHYRX_INPUT_ENS_REG1_MEM_OVRD_EN_RXDLDO_RESETVAL  (0x00000000U)
#define CSL_PCIEPHYRX_INPUT_ENS_REG1_MEM_OVRD_EN_RXDLDO_MAX     (0x00000001U)

#define CSL_PCIEPHYRX_INPUT_ENS_REG1_MEM_EN_RXTERM_MASK         (0x00800000U)
#define CSL_PCIEPHYRX_INPUT_ENS_REG1_MEM_EN_RXTERM_SHIFT        (23U)
#define CSL_PCIEPHYRX_INPUT_ENS_REG1_MEM_EN_RXTERM_RESETVAL     (0x00000000U)
#define CSL_PCIEPHYRX_INPUT_ENS_REG1_MEM_EN_RXTERM_MAX          (0x00000001U)

#define CSL_PCIEPHYRX_INPUT_ENS_REG1_MEM_OVRD_EN_RXTERM_MASK    (0x00400000U)
#define CSL_PCIEPHYRX_INPUT_ENS_REG1_MEM_OVRD_EN_RXTERM_SHIFT   (22U)
#define CSL_PCIEPHYRX_INPUT_ENS_REG1_MEM_OVRD_EN_RXTERM_RESETVAL  (0x00000000U)
#define CSL_PCIEPHYRX_INPUT_ENS_REG1_MEM_OVRD_EN_RXTERM_MAX     (0x00000001U)

#define CSL_PCIEPHYRX_INPUT_ENS_REG1_MEM_EN_EQ_ANA_MASK         (0x00200000U)
#define CSL_PCIEPHYRX_INPUT_ENS_REG1_MEM_EN_EQ_ANA_SHIFT        (21U)
#define CSL_PCIEPHYRX_INPUT_ENS_REG1_MEM_EN_EQ_ANA_RESETVAL     (0x00000000U)
#define CSL_PCIEPHYRX_INPUT_ENS_REG1_MEM_EN_EQ_ANA_MAX          (0x00000001U)

#define CSL_PCIEPHYRX_INPUT_ENS_REG1_MEM_OVRD_EN_EQ_ANA_MASK    (0x00100000U)
#define CSL_PCIEPHYRX_INPUT_ENS_REG1_MEM_OVRD_EN_EQ_ANA_SHIFT   (20U)
#define CSL_PCIEPHYRX_INPUT_ENS_REG1_MEM_OVRD_EN_EQ_ANA_RESETVAL  (0x00000000U)
#define CSL_PCIEPHYRX_INPUT_ENS_REG1_MEM_OVRD_EN_EQ_ANA_MAX     (0x00000001U)

#define CSL_PCIEPHYRX_INPUT_ENS_REG1_MEM_EN_LOSD_MASK           (0x00080000U)
#define CSL_PCIEPHYRX_INPUT_ENS_REG1_MEM_EN_LOSD_SHIFT          (19U)
#define CSL_PCIEPHYRX_INPUT_ENS_REG1_MEM_EN_LOSD_RESETVAL       (0x00000000U)
#define CSL_PCIEPHYRX_INPUT_ENS_REG1_MEM_EN_LOSD_MAX            (0x00000001U)

#define CSL_PCIEPHYRX_INPUT_ENS_REG1_MEM_OVRD_EN_LOSD_MASK      (0x00040000U)
#define CSL_PCIEPHYRX_INPUT_ENS_REG1_MEM_OVRD_EN_LOSD_SHIFT     (18U)
#define CSL_PCIEPHYRX_INPUT_ENS_REG1_MEM_OVRD_EN_LOSD_RESETVAL  (0x00000000U)
#define CSL_PCIEPHYRX_INPUT_ENS_REG1_MEM_OVRD_EN_LOSD_MAX       (0x00000001U)

#define CSL_PCIEPHYRX_INPUT_ENS_REG1_MEM_EN_PWM_MASK            (0x00020000U)
#define CSL_PCIEPHYRX_INPUT_ENS_REG1_MEM_EN_PWM_SHIFT           (17U)
#define CSL_PCIEPHYRX_INPUT_ENS_REG1_MEM_EN_PWM_RESETVAL        (0x00000000U)
#define CSL_PCIEPHYRX_INPUT_ENS_REG1_MEM_EN_PWM_MAX             (0x00000001U)

#define CSL_PCIEPHYRX_INPUT_ENS_REG1_MEM_OVRD_EN_PWM_MASK       (0x00010000U)
#define CSL_PCIEPHYRX_INPUT_ENS_REG1_MEM_OVRD_EN_PWM_SHIFT      (16U)
#define CSL_PCIEPHYRX_INPUT_ENS_REG1_MEM_OVRD_EN_PWM_RESETVAL   (0x00000000U)
#define CSL_PCIEPHYRX_INPUT_ENS_REG1_MEM_OVRD_EN_PWM_MAX        (0x00000001U)

#define CSL_PCIEPHYRX_INPUT_ENS_REG1_MEM_EN_SYS_MASK            (0x00008000U)
#define CSL_PCIEPHYRX_INPUT_ENS_REG1_MEM_EN_SYS_SHIFT           (15U)
#define CSL_PCIEPHYRX_INPUT_ENS_REG1_MEM_EN_SYS_RESETVAL        (0x00000000U)
#define CSL_PCIEPHYRX_INPUT_ENS_REG1_MEM_EN_SYS_MAX             (0x00000001U)

#define CSL_PCIEPHYRX_INPUT_ENS_REG1_MEM_OVRD_EN_SYS_MASK       (0x00004000U)
#define CSL_PCIEPHYRX_INPUT_ENS_REG1_MEM_OVRD_EN_SYS_SHIFT      (14U)
#define CSL_PCIEPHYRX_INPUT_ENS_REG1_MEM_OVRD_EN_SYS_RESETVAL   (0x00000000U)
#define CSL_PCIEPHYRX_INPUT_ENS_REG1_MEM_OVRD_EN_SYS_MAX        (0x00000001U)

#define CSL_PCIEPHYRX_INPUT_ENS_REG1_MEM_PLL_LOCK_MASK          (0x00002000U)
#define CSL_PCIEPHYRX_INPUT_ENS_REG1_MEM_PLL_LOCK_SHIFT         (13U)
#define CSL_PCIEPHYRX_INPUT_ENS_REG1_MEM_PLL_LOCK_RESETVAL      (0x00000000U)
#define CSL_PCIEPHYRX_INPUT_ENS_REG1_MEM_PLL_LOCK_MAX           (0x00000001U)

#define CSL_PCIEPHYRX_INPUT_ENS_REG1_MEM_OVRD_PLL_LOCK_MASK     (0x00001000U)
#define CSL_PCIEPHYRX_INPUT_ENS_REG1_MEM_OVRD_PLL_LOCK_SHIFT    (12U)
#define CSL_PCIEPHYRX_INPUT_ENS_REG1_MEM_OVRD_PLL_LOCK_RESETVAL  (0x00000000U)
#define CSL_PCIEPHYRX_INPUT_ENS_REG1_MEM_OVRD_PLL_LOCK_MAX      (0x00000001U)

#define CSL_PCIEPHYRX_INPUT_ENS_REG1_MEM_EN_DCC_MASK            (0x00000800U)
#define CSL_PCIEPHYRX_INPUT_ENS_REG1_MEM_EN_DCC_SHIFT           (11U)
#define CSL_PCIEPHYRX_INPUT_ENS_REG1_MEM_EN_DCC_RESETVAL        (0x00000000U)
#define CSL_PCIEPHYRX_INPUT_ENS_REG1_MEM_EN_DCC_MAX             (0x00000001U)

#define CSL_PCIEPHYRX_INPUT_ENS_REG1_MEM_OVRD_EN_DCC_MASK       (0x00000400U)
#define CSL_PCIEPHYRX_INPUT_ENS_REG1_MEM_OVRD_EN_DCC_SHIFT      (10U)
#define CSL_PCIEPHYRX_INPUT_ENS_REG1_MEM_OVRD_EN_DCC_RESETVAL   (0x00000000U)
#define CSL_PCIEPHYRX_INPUT_ENS_REG1_MEM_OVRD_EN_DCC_MAX        (0x00000001U)

#define CSL_PCIEPHYRX_INPUT_ENS_REG1_MEM_EN_DLL_MASK            (0x00000200U)
#define CSL_PCIEPHYRX_INPUT_ENS_REG1_MEM_EN_DLL_SHIFT           (9U)
#define CSL_PCIEPHYRX_INPUT_ENS_REG1_MEM_EN_DLL_RESETVAL        (0x00000000U)
#define CSL_PCIEPHYRX_INPUT_ENS_REG1_MEM_EN_DLL_MAX             (0x00000001U)

#define CSL_PCIEPHYRX_INPUT_ENS_REG1_MEM_OVRD_EN_DLL_MASK       (0x00000100U)
#define CSL_PCIEPHYRX_INPUT_ENS_REG1_MEM_OVRD_EN_DLL_SHIFT      (8U)
#define CSL_PCIEPHYRX_INPUT_ENS_REG1_MEM_OVRD_EN_DLL_RESETVAL   (0x00000000U)
#define CSL_PCIEPHYRX_INPUT_ENS_REG1_MEM_OVRD_EN_DLL_MAX        (0x00000001U)

#define CSL_PCIEPHYRX_INPUT_ENS_REG1_MEM_EN_PREDLL_MASK         (0x00000080U)
#define CSL_PCIEPHYRX_INPUT_ENS_REG1_MEM_EN_PREDLL_SHIFT        (7U)
#define CSL_PCIEPHYRX_INPUT_ENS_REG1_MEM_EN_PREDLL_RESETVAL     (0x00000000U)
#define CSL_PCIEPHYRX_INPUT_ENS_REG1_MEM_EN_PREDLL_MAX          (0x00000001U)

#define CSL_PCIEPHYRX_INPUT_ENS_REG1_MEM_OVRD_EN_PREDLL_MASK    (0x00000040U)
#define CSL_PCIEPHYRX_INPUT_ENS_REG1_MEM_OVRD_EN_PREDLL_SHIFT   (6U)
#define CSL_PCIEPHYRX_INPUT_ENS_REG1_MEM_OVRD_EN_PREDLL_RESETVAL  (0x00000000U)
#define CSL_PCIEPHYRX_INPUT_ENS_REG1_MEM_OVRD_EN_PREDLL_MAX     (0x00000001U)

#define CSL_PCIEPHYRX_INPUT_ENS_REG1_MEM_EN_PHINT_MASK          (0x00000020U)
#define CSL_PCIEPHYRX_INPUT_ENS_REG1_MEM_EN_PHINT_SHIFT         (5U)
#define CSL_PCIEPHYRX_INPUT_ENS_REG1_MEM_EN_PHINT_RESETVAL      (0x00000000U)
#define CSL_PCIEPHYRX_INPUT_ENS_REG1_MEM_EN_PHINT_MAX           (0x00000001U)

#define CSL_PCIEPHYRX_INPUT_ENS_REG1_MEM_OVRD_EN_PHINT_MASK     (0x00000010U)
#define CSL_PCIEPHYRX_INPUT_ENS_REG1_MEM_OVRD_EN_PHINT_SHIFT    (4U)
#define CSL_PCIEPHYRX_INPUT_ENS_REG1_MEM_OVRD_EN_PHINT_RESETVAL  (0x00000000U)
#define CSL_PCIEPHYRX_INPUT_ENS_REG1_MEM_OVRD_EN_PHINT_MAX      (0x00000001U)

#define CSL_PCIEPHYRX_INPUT_ENS_REG1_MEM_EN_DLLTRIM_MASK        (0x00000008U)
#define CSL_PCIEPHYRX_INPUT_ENS_REG1_MEM_EN_DLLTRIM_SHIFT       (3U)
#define CSL_PCIEPHYRX_INPUT_ENS_REG1_MEM_EN_DLLTRIM_RESETVAL    (0x00000000U)
#define CSL_PCIEPHYRX_INPUT_ENS_REG1_MEM_EN_DLLTRIM_MAX         (0x00000001U)

#define CSL_PCIEPHYRX_INPUT_ENS_REG1_MEM_OVRD_EN_DLLTRIM_MASK   (0x00000004U)
#define CSL_PCIEPHYRX_INPUT_ENS_REG1_MEM_OVRD_EN_DLLTRIM_SHIFT  (2U)
#define CSL_PCIEPHYRX_INPUT_ENS_REG1_MEM_OVRD_EN_DLLTRIM_RESETVAL  (0x00000000U)
#define CSL_PCIEPHYRX_INPUT_ENS_REG1_MEM_OVRD_EN_DLLTRIM_MAX    (0x00000001U)

#define CSL_PCIEPHYRX_INPUT_ENS_REG1_MEM_EN_BGTRIM_MASK         (0x00000002U)
#define CSL_PCIEPHYRX_INPUT_ENS_REG1_MEM_EN_BGTRIM_SHIFT        (1U)
#define CSL_PCIEPHYRX_INPUT_ENS_REG1_MEM_EN_BGTRIM_RESETVAL     (0x00000000U)
#define CSL_PCIEPHYRX_INPUT_ENS_REG1_MEM_EN_BGTRIM_MAX          (0x00000001U)

#define CSL_PCIEPHYRX_INPUT_ENS_REG1_MEM_SPAREBITS_GANGARX_INPUT_ENS_REG1_MASK  (0x00000001U)
#define CSL_PCIEPHYRX_INPUT_ENS_REG1_MEM_SPAREBITS_GANGARX_INPUT_ENS_REG1_SHIFT  (0U)
#define CSL_PCIEPHYRX_INPUT_ENS_REG1_MEM_SPAREBITS_GANGARX_INPUT_ENS_REG1_RESETVAL  (0x00000000U)
#define CSL_PCIEPHYRX_INPUT_ENS_REG1_MEM_SPAREBITS_GANGARX_INPUT_ENS_REG1_MAX  (0x00000001U)

#define CSL_PCIEPHYRX_INPUT_ENS_REG1_RESETVAL                   (0x00000000U)

/* INPUT_ENS_REG2 */

#define CSL_PCIEPHYRX_INPUT_ENS_REG2_MEM_EN_RXD_MASK            (0x80000000U)
#define CSL_PCIEPHYRX_INPUT_ENS_REG2_MEM_EN_RXD_SHIFT           (31U)
#define CSL_PCIEPHYRX_INPUT_ENS_REG2_MEM_EN_RXD_RESETVAL        (0x00000000U)
#define CSL_PCIEPHYRX_INPUT_ENS_REG2_MEM_EN_RXD_MAX             (0x00000001U)

#define CSL_PCIEPHYRX_INPUT_ENS_REG2_MEM_OVRD_EN_RXD_MASK       (0x40000000U)
#define CSL_PCIEPHYRX_INPUT_ENS_REG2_MEM_OVRD_EN_RXD_SHIFT      (30U)
#define CSL_PCIEPHYRX_INPUT_ENS_REG2_MEM_OVRD_EN_RXD_RESETVAL   (0x00000000U)
#define CSL_PCIEPHYRX_INPUT_ENS_REG2_MEM_OVRD_EN_RXD_MAX        (0x00000001U)

#define CSL_PCIEPHYRX_INPUT_ENS_REG2_MEM_EN_EQ_DIG_MASK         (0x20000000U)
#define CSL_PCIEPHYRX_INPUT_ENS_REG2_MEM_EN_EQ_DIG_SHIFT        (29U)
#define CSL_PCIEPHYRX_INPUT_ENS_REG2_MEM_EN_EQ_DIG_RESETVAL     (0x00000000U)
#define CSL_PCIEPHYRX_INPUT_ENS_REG2_MEM_EN_EQ_DIG_MAX          (0x00000001U)

#define CSL_PCIEPHYRX_INPUT_ENS_REG2_MEM_OVRD_EN_EQ_DIG_MASK    (0x10000000U)
#define CSL_PCIEPHYRX_INPUT_ENS_REG2_MEM_OVRD_EN_EQ_DIG_SHIFT   (28U)
#define CSL_PCIEPHYRX_INPUT_ENS_REG2_MEM_OVRD_EN_EQ_DIG_RESETVAL  (0x00000000U)
#define CSL_PCIEPHYRX_INPUT_ENS_REG2_MEM_OVRD_EN_EQ_DIG_MAX     (0x00000001U)

#define CSL_PCIEPHYRX_INPUT_ENS_REG2_MEM_EN_SAOC_DIG_MASK       (0x08000000U)
#define CSL_PCIEPHYRX_INPUT_ENS_REG2_MEM_EN_SAOC_DIG_SHIFT      (27U)
#define CSL_PCIEPHYRX_INPUT_ENS_REG2_MEM_EN_SAOC_DIG_RESETVAL   (0x00000000U)
#define CSL_PCIEPHYRX_INPUT_ENS_REG2_MEM_EN_SAOC_DIG_MAX        (0x00000001U)

#define CSL_PCIEPHYRX_INPUT_ENS_REG2_MEM_OVRD_EN_SAOC_DIG_MASK  (0x04000000U)
#define CSL_PCIEPHYRX_INPUT_ENS_REG2_MEM_OVRD_EN_SAOC_DIG_SHIFT  (26U)
#define CSL_PCIEPHYRX_INPUT_ENS_REG2_MEM_OVRD_EN_SAOC_DIG_RESETVAL  (0x00000000U)
#define CSL_PCIEPHYRX_INPUT_ENS_REG2_MEM_OVRD_EN_SAOC_DIG_MAX   (0x00000001U)

#define CSL_PCIEPHYRX_INPUT_ENS_REG2_MEM_RXALDO_STBL_IN_MASK    (0x02000000U)
#define CSL_PCIEPHYRX_INPUT_ENS_REG2_MEM_RXALDO_STBL_IN_SHIFT   (25U)
#define CSL_PCIEPHYRX_INPUT_ENS_REG2_MEM_RXALDO_STBL_IN_RESETVAL  (0x00000000U)
#define CSL_PCIEPHYRX_INPUT_ENS_REG2_MEM_RXALDO_STBL_IN_MAX     (0x00000001U)

#define CSL_PCIEPHYRX_INPUT_ENS_REG2_MEM_OVRD_RXALDO_STBL_IN_MASK  (0x01000000U)
#define CSL_PCIEPHYRX_INPUT_ENS_REG2_MEM_OVRD_RXALDO_STBL_IN_SHIFT  (24U)
#define CSL_PCIEPHYRX_INPUT_ENS_REG2_MEM_OVRD_RXALDO_STBL_IN_RESETVAL  (0x00000000U)
#define CSL_PCIEPHYRX_INPUT_ENS_REG2_MEM_OVRD_RXALDO_STBL_IN_MAX  (0x00000001U)

#define CSL_PCIEPHYRX_INPUT_ENS_REG2_MEM_RXDLDO_STBL_IN_MASK    (0x00800000U)
#define CSL_PCIEPHYRX_INPUT_ENS_REG2_MEM_RXDLDO_STBL_IN_SHIFT   (23U)
#define CSL_PCIEPHYRX_INPUT_ENS_REG2_MEM_RXDLDO_STBL_IN_RESETVAL  (0x00000000U)
#define CSL_PCIEPHYRX_INPUT_ENS_REG2_MEM_RXDLDO_STBL_IN_MAX     (0x00000001U)

#define CSL_PCIEPHYRX_INPUT_ENS_REG2_MEM_OVRD_RXDLDO_STBL_IN_MASK  (0x00400000U)
#define CSL_PCIEPHYRX_INPUT_ENS_REG2_MEM_OVRD_RXDLDO_STBL_IN_SHIFT  (22U)
#define CSL_PCIEPHYRX_INPUT_ENS_REG2_MEM_OVRD_RXDLDO_STBL_IN_RESETVAL  (0x00000000U)
#define CSL_PCIEPHYRX_INPUT_ENS_REG2_MEM_OVRD_RXDLDO_STBL_IN_MAX  (0x00000001U)

#define CSL_PCIEPHYRX_INPUT_ENS_REG2_MEM_SPAREBITS_GANGARX_INPUT_ENS_REG2_MASK  (0x003FFFFFU)
#define CSL_PCIEPHYRX_INPUT_ENS_REG2_MEM_SPAREBITS_GANGARX_INPUT_ENS_REG2_SHIFT  (0U)
#define CSL_PCIEPHYRX_INPUT_ENS_REG2_MEM_SPAREBITS_GANGARX_INPUT_ENS_REG2_RESETVAL  (0x00000000U)
#define CSL_PCIEPHYRX_INPUT_ENS_REG2_MEM_SPAREBITS_GANGARX_INPUT_ENS_REG2_MAX  (0x003fffffU)

#define CSL_PCIEPHYRX_INPUT_ENS_REG2_RESETVAL                   (0x00000000U)

/* LDO_CTRL_REG1 */

#define CSL_PCIEPHYRX_LDO_CTRL_REG1_MEM_RXALDO_CTRL_MASK        (0xFFFF0000U)
#define CSL_PCIEPHYRX_LDO_CTRL_REG1_MEM_RXALDO_CTRL_SHIFT       (16U)
#define CSL_PCIEPHYRX_LDO_CTRL_REG1_MEM_RXALDO_CTRL_RESETVAL    (0x00000000U)
#define CSL_PCIEPHYRX_LDO_CTRL_REG1_MEM_RXALDO_CTRL_MAX         (0x0000ffffU)

#define CSL_PCIEPHYRX_LDO_CTRL_REG1_MEM_RXDLDO_CTRL_MASK        (0x0000FFFFU)
#define CSL_PCIEPHYRX_LDO_CTRL_REG1_MEM_RXDLDO_CTRL_SHIFT       (0U)
#define CSL_PCIEPHYRX_LDO_CTRL_REG1_MEM_RXDLDO_CTRL_RESETVAL    (0x00000000U)
#define CSL_PCIEPHYRX_LDO_CTRL_REG1_MEM_RXDLDO_CTRL_MAX         (0x0000ffffU)

#define CSL_PCIEPHYRX_LDO_CTRL_REG1_RESETVAL                    (0x00000000U)

/* ANA_PROGRAMMABILITY_REG1 */

#define CSL_PCIEPHYRX_ANA_PROGRAMMABILITY_REG1_MEM_ANATESTMODE_MASK  (0xFFFFFF00U)
#define CSL_PCIEPHYRX_ANA_PROGRAMMABILITY_REG1_MEM_ANATESTMODE_SHIFT  (8U)
#define CSL_PCIEPHYRX_ANA_PROGRAMMABILITY_REG1_MEM_ANATESTMODE_RESETVAL  (0x00000000U)
#define CSL_PCIEPHYRX_ANA_PROGRAMMABILITY_REG1_MEM_ANATESTMODE_MAX  (0x00ffffffU)

#define CSL_PCIEPHYRX_ANA_PROGRAMMABILITY_REG1_MEM_EN_PLLBYP_MASK  (0x00000080U)
#define CSL_PCIEPHYRX_ANA_PROGRAMMABILITY_REG1_MEM_EN_PLLBYP_SHIFT  (7U)
#define CSL_PCIEPHYRX_ANA_PROGRAMMABILITY_REG1_MEM_EN_PLLBYP_RESETVAL  (0x00000000U)
#define CSL_PCIEPHYRX_ANA_PROGRAMMABILITY_REG1_MEM_EN_PLLBYP_MAX  (0x00000001U)

#define CSL_PCIEPHYRX_ANA_PROGRAMMABILITY_REG1_MEM_PLLDIV_MASK  (0x00000060U)
#define CSL_PCIEPHYRX_ANA_PROGRAMMABILITY_REG1_MEM_PLLDIV_SHIFT  (5U)
#define CSL_PCIEPHYRX_ANA_PROGRAMMABILITY_REG1_MEM_PLLDIV_RESETVAL  (0x00000000U)
#define CSL_PCIEPHYRX_ANA_PROGRAMMABILITY_REG1_MEM_PLLDIV_MAX   (0x00000003U)

#define CSL_PCIEPHYRX_ANA_PROGRAMMABILITY_REG1_MEM_SPAREBITS_GANGARX_ANA_PROGRAMMABILITY_REG1_MASK  (0x0000001FU)
#define CSL_PCIEPHYRX_ANA_PROGRAMMABILITY_REG1_MEM_SPAREBITS_GANGARX_ANA_PROGRAMMABILITY_REG1_SHIFT  (0U)
#define CSL_PCIEPHYRX_ANA_PROGRAMMABILITY_REG1_MEM_SPAREBITS_GANGARX_ANA_PROGRAMMABILITY_REG1_RESETVAL  (0x00000000U)
#define CSL_PCIEPHYRX_ANA_PROGRAMMABILITY_REG1_MEM_SPAREBITS_GANGARX_ANA_PROGRAMMABILITY_REG1_MAX  (0x0000001fU)

#define CSL_PCIEPHYRX_ANA_PROGRAMMABILITY_REG1_RESETVAL         (0x00000000U)

/* TRIM_REG1 */

#define CSL_PCIEPHYRX_TRIM_REG1_MEM_BGTRIM_MASK                 (0xFFFF0000U)
#define CSL_PCIEPHYRX_TRIM_REG1_MEM_BGTRIM_SHIFT                (16U)
#define CSL_PCIEPHYRX_TRIM_REG1_MEM_BGTRIM_RESETVAL             (0x00000000U)
#define CSL_PCIEPHYRX_TRIM_REG1_MEM_BGTRIM_MAX                  (0x0000ffffU)

#define CSL_PCIEPHYRX_TRIM_REG1_MEM_OVRD_EFUSE_BGTRIM_MASK      (0x00008000U)
#define CSL_PCIEPHYRX_TRIM_REG1_MEM_OVRD_EFUSE_BGTRIM_SHIFT     (15U)
#define CSL_PCIEPHYRX_TRIM_REG1_MEM_OVRD_EFUSE_BGTRIM_RESETVAL  (0x00000000U)
#define CSL_PCIEPHYRX_TRIM_REG1_MEM_OVRD_EFUSE_BGTRIM_MAX       (0x00000001U)

#define CSL_PCIEPHYRX_TRIM_REG1_MEM_SPAREBITS_GANGARX_TRIM_REG1_MASK  (0x00007FFFU)
#define CSL_PCIEPHYRX_TRIM_REG1_MEM_SPAREBITS_GANGARX_TRIM_REG1_SHIFT  (0U)
#define CSL_PCIEPHYRX_TRIM_REG1_MEM_SPAREBITS_GANGARX_TRIM_REG1_RESETVAL  (0x00000000U)
#define CSL_PCIEPHYRX_TRIM_REG1_MEM_SPAREBITS_GANGARX_TRIM_REG1_MAX  (0x00007fffU)

#define CSL_PCIEPHYRX_TRIM_REG1_RESETVAL                        (0x00000000U)

/* TRIM_REG2 */

#define CSL_PCIEPHYRX_TRIM_REG2_MEM_RXTRIM_MASK                 (0xF8000000U)
#define CSL_PCIEPHYRX_TRIM_REG2_MEM_RXTRIM_SHIFT                (27U)
#define CSL_PCIEPHYRX_TRIM_REG2_MEM_RXTRIM_RESETVAL             (0x00000000U)
#define CSL_PCIEPHYRX_TRIM_REG2_MEM_RXTRIM_MAX                  (0x0000001fU)

#define CSL_PCIEPHYRX_TRIM_REG2_MEM_OVRD_EFUSE_RXTRIM_MASK      (0x04000000U)
#define CSL_PCIEPHYRX_TRIM_REG2_MEM_OVRD_EFUSE_RXTRIM_SHIFT     (26U)
#define CSL_PCIEPHYRX_TRIM_REG2_MEM_OVRD_EFUSE_RXTRIM_RESETVAL  (0x00000000U)
#define CSL_PCIEPHYRX_TRIM_REG2_MEM_OVRD_EFUSE_RXTRIM_MAX       (0x00000001U)

#define CSL_PCIEPHYRX_TRIM_REG2_MEM_SPAREBITS_GANGARX_TRIM_REG2_MASK  (0x03FFFFFFU)
#define CSL_PCIEPHYRX_TRIM_REG2_MEM_SPAREBITS_GANGARX_TRIM_REG2_SHIFT  (0U)
#define CSL_PCIEPHYRX_TRIM_REG2_MEM_SPAREBITS_GANGARX_TRIM_REG2_RESETVAL  (0x00000000U)
#define CSL_PCIEPHYRX_TRIM_REG2_MEM_SPAREBITS_GANGARX_TRIM_REG2_MAX  (0x03ffffffU)

#define CSL_PCIEPHYRX_TRIM_REG2_RESETVAL                        (0x00000000U)

/* TRIM_REG3 */

#define CSL_PCIEPHYRX_TRIM_REG3_MEM_LOSTRIM_MASK                (0xF0000000U)
#define CSL_PCIEPHYRX_TRIM_REG3_MEM_LOSTRIM_SHIFT               (28U)
#define CSL_PCIEPHYRX_TRIM_REG3_MEM_LOSTRIM_RESETVAL            (0x00000000U)
#define CSL_PCIEPHYRX_TRIM_REG3_MEM_LOSTRIM_MAX                 (0x0000000fU)

#define CSL_PCIEPHYRX_TRIM_REG3_MEM_OVRD_EFUSE_LOSTRIM_MASK     (0x08000000U)
#define CSL_PCIEPHYRX_TRIM_REG3_MEM_OVRD_EFUSE_LOSTRIM_SHIFT    (27U)
#define CSL_PCIEPHYRX_TRIM_REG3_MEM_OVRD_EFUSE_LOSTRIM_RESETVAL  (0x00000000U)
#define CSL_PCIEPHYRX_TRIM_REG3_MEM_OVRD_EFUSE_LOSTRIM_MAX      (0x00000001U)

#define CSL_PCIEPHYRX_TRIM_REG3_MEM_SPAREBITS_GANGARX_TRIM_REG3_MASK  (0x07FFFFFFU)
#define CSL_PCIEPHYRX_TRIM_REG3_MEM_SPAREBITS_GANGARX_TRIM_REG3_SHIFT  (0U)
#define CSL_PCIEPHYRX_TRIM_REG3_MEM_SPAREBITS_GANGARX_TRIM_REG3_RESETVAL  (0x00000000U)
#define CSL_PCIEPHYRX_TRIM_REG3_MEM_SPAREBITS_GANGARX_TRIM_REG3_MAX  (0x07ffffffU)

#define CSL_PCIEPHYRX_TRIM_REG3_RESETVAL                        (0x00000000U)

/* TRIM_REG4 */

#define CSL_PCIEPHYRX_TRIM_REG4_MEM_DLL_TRIM_SEL_MASK           (0xC0000000U)
#define CSL_PCIEPHYRX_TRIM_REG4_MEM_DLL_TRIM_SEL_SHIFT          (30U)
#define CSL_PCIEPHYRX_TRIM_REG4_MEM_DLL_TRIM_SEL_RESETVAL       (0x00000000U)
#define CSL_PCIEPHYRX_TRIM_REG4_MEM_DLL_TRIM_SEL_MAX            (0x00000003U)

#define CSL_PCIEPHYRX_TRIM_REG4_MEM_DLLCOARSETRIM_MASK          (0x3C000000U)
#define CSL_PCIEPHYRX_TRIM_REG4_MEM_DLLCOARSETRIM_SHIFT         (26U)
#define CSL_PCIEPHYRX_TRIM_REG4_MEM_DLLCOARSETRIM_RESETVAL      (0x00000000U)
#define CSL_PCIEPHYRX_TRIM_REG4_MEM_DLLCOARSETRIM_MAX           (0x0000000fU)

#define CSL_PCIEPHYRX_TRIM_REG4_MEM_OVRD_EFUSE_DLLCOARSETRIM_MASK  (0x02000000U)
#define CSL_PCIEPHYRX_TRIM_REG4_MEM_OVRD_EFUSE_DLLCOARSETRIM_SHIFT  (25U)
#define CSL_PCIEPHYRX_TRIM_REG4_MEM_OVRD_EFUSE_DLLCOARSETRIM_RESETVAL  (0x00000000U)
#define CSL_PCIEPHYRX_TRIM_REG4_MEM_OVRD_EFUSE_DLLCOARSETRIM_MAX  (0x00000001U)

#define CSL_PCIEPHYRX_TRIM_REG4_MEM_SPAREBITS_GANGARX_TRIM_REG4_MASK  (0x01FFFFFFU)
#define CSL_PCIEPHYRX_TRIM_REG4_MEM_SPAREBITS_GANGARX_TRIM_REG4_SHIFT  (0U)
#define CSL_PCIEPHYRX_TRIM_REG4_MEM_SPAREBITS_GANGARX_TRIM_REG4_RESETVAL  (0x00000000U)
#define CSL_PCIEPHYRX_TRIM_REG4_MEM_SPAREBITS_GANGARX_TRIM_REG4_MAX  (0x01ffffffU)

#define CSL_PCIEPHYRX_TRIM_REG4_RESETVAL                        (0x00000000U)

/* TRIM_OBSERVE_REG1 */

#define CSL_PCIEPHYRX_TRIM_OBSERVE_REG1_DLLOFFSET_CALIBOUT_RD_MASK  (0xFC000000U)
#define CSL_PCIEPHYRX_TRIM_OBSERVE_REG1_DLLOFFSET_CALIBOUT_RD_SHIFT  (26U)
#define CSL_PCIEPHYRX_TRIM_OBSERVE_REG1_DLLOFFSET_CALIBOUT_RD_RESETVAL  (0x00000000U)
#define CSL_PCIEPHYRX_TRIM_OBSERVE_REG1_DLLOFFSET_CALIBOUT_RD_MAX  (0x0000003fU)

#define CSL_PCIEPHYRX_TRIM_OBSERVE_REG1_DLLCOARSE_CALIBOUT_RD_MASK  (0x03C00000U)
#define CSL_PCIEPHYRX_TRIM_OBSERVE_REG1_DLLCOARSE_CALIBOUT_RD_SHIFT  (22U)
#define CSL_PCIEPHYRX_TRIM_OBSERVE_REG1_DLLCOARSE_CALIBOUT_RD_RESETVAL  (0x00000000U)
#define CSL_PCIEPHYRX_TRIM_OBSERVE_REG1_DLLCOARSE_CALIBOUT_RD_MAX  (0x0000000fU)

#define CSL_PCIEPHYRX_TRIM_OBSERVE_REG1_SPAREBITS_GANGARX_TRIM_OBSERVE_REG1_MASK  (0x003FFFFFU)
#define CSL_PCIEPHYRX_TRIM_OBSERVE_REG1_SPAREBITS_GANGARX_TRIM_OBSERVE_REG1_SHIFT  (0U)
#define CSL_PCIEPHYRX_TRIM_OBSERVE_REG1_SPAREBITS_GANGARX_TRIM_OBSERVE_REG1_RESETVAL  (0x00000000U)
#define CSL_PCIEPHYRX_TRIM_OBSERVE_REG1_SPAREBITS_GANGARX_TRIM_OBSERVE_REG1_MAX  (0x003fffffU)

#define CSL_PCIEPHYRX_TRIM_OBSERVE_REG1_RESETVAL                (0x00000000U)

/* DLL_REG1 */

#define CSL_PCIEPHYRX_DLL_REG1_MEM_DLL_PHINT_RATE_MASK          (0xC0000000U)
#define CSL_PCIEPHYRX_DLL_REG1_MEM_DLL_PHINT_RATE_SHIFT         (30U)
#define CSL_PCIEPHYRX_DLL_REG1_MEM_DLL_PHINT_RATE_RESETVAL      (0x00000003U)
#define CSL_PCIEPHYRX_DLL_REG1_MEM_DLL_PHINT_RATE_MAX           (0x00000003U)

#define CSL_PCIEPHYRX_DLL_REG1_MEM_DLL_OC_ITER_STL_MASK         (0x3FF00000U)
#define CSL_PCIEPHYRX_DLL_REG1_MEM_DLL_OC_ITER_STL_SHIFT        (20U)
#define CSL_PCIEPHYRX_DLL_REG1_MEM_DLL_OC_ITER_STL_RESETVAL     (0x0000000aU)
#define CSL_PCIEPHYRX_DLL_REG1_MEM_DLL_OC_ITER_STL_MAX          (0x000003ffU)

#define CSL_PCIEPHYRX_DLL_REG1_MEM_DLL_OC_INIT_LOG2_STL_MASK    (0x000E0000U)
#define CSL_PCIEPHYRX_DLL_REG1_MEM_DLL_OC_INIT_LOG2_STL_SHIFT   (17U)
#define CSL_PCIEPHYRX_DLL_REG1_MEM_DLL_OC_INIT_LOG2_STL_RESETVAL  (0x00000002U)
#define CSL_PCIEPHYRX_DLL_REG1_MEM_DLL_OC_INIT_LOG2_STL_MAX     (0x00000007U)

#define CSL_PCIEPHYRX_DLL_REG1_MEM_DLL_CC_ITER_STL_MASK         (0x0001FF80U)
#define CSL_PCIEPHYRX_DLL_REG1_MEM_DLL_CC_ITER_STL_SHIFT        (7U)
#define CSL_PCIEPHYRX_DLL_REG1_MEM_DLL_CC_ITER_STL_RESETVAL     (0x00000032U)
#define CSL_PCIEPHYRX_DLL_REG1_MEM_DLL_CC_ITER_STL_MAX          (0x000003ffU)

#define CSL_PCIEPHYRX_DLL_REG1_MEM_DLL_CC_INIT_LOG2_STL_MASK    (0x00000070U)
#define CSL_PCIEPHYRX_DLL_REG1_MEM_DLL_CC_INIT_LOG2_STL_SHIFT   (4U)
#define CSL_PCIEPHYRX_DLL_REG1_MEM_DLL_CC_INIT_LOG2_STL_RESETVAL  (0x00000001U)
#define CSL_PCIEPHYRX_DLL_REG1_MEM_DLL_CC_INIT_LOG2_STL_MAX     (0x00000007U)

#define CSL_PCIEPHYRX_DLL_REG1_MEM_DLL_CC_INIT_CODE_MASK        (0x0000000FU)
#define CSL_PCIEPHYRX_DLL_REG1_MEM_DLL_CC_INIT_CODE_SHIFT       (0U)
#define CSL_PCIEPHYRX_DLL_REG1_MEM_DLL_CC_INIT_CODE_RESETVAL    (0x00000005U)
#define CSL_PCIEPHYRX_DLL_REG1_MEM_DLL_CC_INIT_CODE_MAX         (0x0000000fU)

#define CSL_PCIEPHYRX_DLL_REG1_RESETVAL                         (0xc0a41915U)

/* DIGITAL_MODES_REG1 */

#define CSL_PCIEPHYRX_DIGITAL_MODES_REG1_MEM_INV_RXPN_PAIR_MASK  (0x80000000U)
#define CSL_PCIEPHYRX_DIGITAL_MODES_REG1_MEM_INV_RXPN_PAIR_SHIFT  (31U)
#define CSL_PCIEPHYRX_DIGITAL_MODES_REG1_MEM_INV_RXPN_PAIR_RESETVAL  (0x00000000U)
#define CSL_PCIEPHYRX_DIGITAL_MODES_REG1_MEM_INV_RXPN_PAIR_MAX  (0x00000001U)

#define CSL_PCIEPHYRX_DIGITAL_MODES_REG1_MEM_OVRD_INV_RXPN_PAIR_MASK  (0x40000000U)
#define CSL_PCIEPHYRX_DIGITAL_MODES_REG1_MEM_OVRD_INV_RXPN_PAIR_SHIFT  (30U)
#define CSL_PCIEPHYRX_DIGITAL_MODES_REG1_MEM_OVRD_INV_RXPN_PAIR_RESETVAL  (0x00000000U)
#define CSL_PCIEPHYRX_DIGITAL_MODES_REG1_MEM_OVRD_INV_RXPN_PAIR_MAX  (0x00000001U)

#define CSL_PCIEPHYRX_DIGITAL_MODES_REG1_MEM_EN8_MASK           (0x20000000U)
#define CSL_PCIEPHYRX_DIGITAL_MODES_REG1_MEM_EN8_SHIFT          (29U)
#define CSL_PCIEPHYRX_DIGITAL_MODES_REG1_MEM_EN8_RESETVAL       (0x00000000U)
#define CSL_PCIEPHYRX_DIGITAL_MODES_REG1_MEM_EN8_MAX            (0x00000001U)

#define CSL_PCIEPHYRX_DIGITAL_MODES_REG1_MEM_HS_RATE_MASK       (0x18000000U)
#define CSL_PCIEPHYRX_DIGITAL_MODES_REG1_MEM_HS_RATE_SHIFT      (27U)
#define CSL_PCIEPHYRX_DIGITAL_MODES_REG1_MEM_HS_RATE_RESETVAL   (0x00000000U)
#define CSL_PCIEPHYRX_DIGITAL_MODES_REG1_MEM_HS_RATE_MAX        (0x00000003U)

#define CSL_PCIEPHYRX_DIGITAL_MODES_REG1_MEM_OVRD_HS_RATE_MASK  (0x04000000U)
#define CSL_PCIEPHYRX_DIGITAL_MODES_REG1_MEM_OVRD_HS_RATE_SHIFT  (26U)
#define CSL_PCIEPHYRX_DIGITAL_MODES_REG1_MEM_OVRD_HS_RATE_RESETVAL  (0x00000000U)
#define CSL_PCIEPHYRX_DIGITAL_MODES_REG1_MEM_OVRD_HS_RATE_MAX   (0x00000001U)

#define CSL_PCIEPHYRX_DIGITAL_MODES_REG1_MEM_ENCOMMA_MASK       (0x02000000U)
#define CSL_PCIEPHYRX_DIGITAL_MODES_REG1_MEM_ENCOMMA_SHIFT      (25U)
#define CSL_PCIEPHYRX_DIGITAL_MODES_REG1_MEM_ENCOMMA_RESETVAL   (0x00000001U)
#define CSL_PCIEPHYRX_DIGITAL_MODES_REG1_MEM_ENCOMMA_MAX        (0x00000001U)

#define CSL_PCIEPHYRX_DIGITAL_MODES_REG1_MEM_ENJOG_MASK         (0x01000000U)
#define CSL_PCIEPHYRX_DIGITAL_MODES_REG1_MEM_ENJOG_SHIFT        (24U)
#define CSL_PCIEPHYRX_DIGITAL_MODES_REG1_MEM_ENJOG_RESETVAL     (0x00000000U)
#define CSL_PCIEPHYRX_DIGITAL_MODES_REG1_MEM_ENJOG_MAX          (0x00000001U)

#define CSL_PCIEPHYRX_DIGITAL_MODES_REG1_MEM_CDR_FASTLOCK_MASK  (0x00800000U)
#define CSL_PCIEPHYRX_DIGITAL_MODES_REG1_MEM_CDR_FASTLOCK_SHIFT  (23U)
#define CSL_PCIEPHYRX_DIGITAL_MODES_REG1_MEM_CDR_FASTLOCK_RESETVAL  (0x00000001U)
#define CSL_PCIEPHYRX_DIGITAL_MODES_REG1_MEM_CDR_FASTLOCK_MAX   (0x00000001U)

#define CSL_PCIEPHYRX_DIGITAL_MODES_REG1_MEM_CDR_LBW_MASK       (0x00600000U)
#define CSL_PCIEPHYRX_DIGITAL_MODES_REG1_MEM_CDR_LBW_SHIFT      (21U)
#define CSL_PCIEPHYRX_DIGITAL_MODES_REG1_MEM_CDR_LBW_RESETVAL   (0x00000003U)
#define CSL_PCIEPHYRX_DIGITAL_MODES_REG1_MEM_CDR_LBW_MAX        (0x00000003U)

#define CSL_PCIEPHYRX_DIGITAL_MODES_REG1_MEM_CDR_STEPCNT_MASK   (0x00180000U)
#define CSL_PCIEPHYRX_DIGITAL_MODES_REG1_MEM_CDR_STEPCNT_SHIFT  (19U)
#define CSL_PCIEPHYRX_DIGITAL_MODES_REG1_MEM_CDR_STEPCNT_RESETVAL  (0x00000000U)
#define CSL_PCIEPHYRX_DIGITAL_MODES_REG1_MEM_CDR_STEPCNT_MAX    (0x00000003U)

#define CSL_PCIEPHYRX_DIGITAL_MODES_REG1_MEM_CDR_STL_MASK       (0x00070000U)
#define CSL_PCIEPHYRX_DIGITAL_MODES_REG1_MEM_CDR_STL_SHIFT      (16U)
#define CSL_PCIEPHYRX_DIGITAL_MODES_REG1_MEM_CDR_STL_RESETVAL   (0x00000003U)
#define CSL_PCIEPHYRX_DIGITAL_MODES_REG1_MEM_CDR_STL_MAX        (0x00000007U)

#define CSL_PCIEPHYRX_DIGITAL_MODES_REG1_MEM_CDR_THR_MASK       (0x0000E000U)
#define CSL_PCIEPHYRX_DIGITAL_MODES_REG1_MEM_CDR_THR_SHIFT      (13U)
#define CSL_PCIEPHYRX_DIGITAL_MODES_REG1_MEM_CDR_THR_RESETVAL   (0x00000001U)
#define CSL_PCIEPHYRX_DIGITAL_MODES_REG1_MEM_CDR_THR_MAX        (0x00000007U)

#define CSL_PCIEPHYRX_DIGITAL_MODES_REG1_MEM_CDR_THR_MODE_MASK  (0x00001000U)
#define CSL_PCIEPHYRX_DIGITAL_MODES_REG1_MEM_CDR_THR_MODE_SHIFT  (12U)
#define CSL_PCIEPHYRX_DIGITAL_MODES_REG1_MEM_CDR_THR_MODE_RESETVAL  (0x00000001U)
#define CSL_PCIEPHYRX_DIGITAL_MODES_REG1_MEM_CDR_THR_MODE_MAX   (0x00000001U)

#define CSL_PCIEPHYRX_DIGITAL_MODES_REG1_MEM_CDR_2NDO_SDM_MODE_MASK  (0x00000800U)
#define CSL_PCIEPHYRX_DIGITAL_MODES_REG1_MEM_CDR_2NDO_SDM_MODE_SHIFT  (11U)
#define CSL_PCIEPHYRX_DIGITAL_MODES_REG1_MEM_CDR_2NDO_SDM_MODE_RESETVAL  (0x00000000U)
#define CSL_PCIEPHYRX_DIGITAL_MODES_REG1_MEM_CDR_2NDO_SDM_MODE_MAX  (0x00000001U)

#define CSL_PCIEPHYRX_DIGITAL_MODES_REG1_MEM_PWM_RATE_MASK      (0x00000780U)
#define CSL_PCIEPHYRX_DIGITAL_MODES_REG1_MEM_PWM_RATE_SHIFT     (7U)
#define CSL_PCIEPHYRX_DIGITAL_MODES_REG1_MEM_PWM_RATE_RESETVAL  (0x00000000U)
#define CSL_PCIEPHYRX_DIGITAL_MODES_REG1_MEM_PWM_RATE_MAX       (0x0000000fU)

#define CSL_PCIEPHYRX_DIGITAL_MODES_REG1_MEM_OVRD_PWM_RATE_MASK  (0x00000040U)
#define CSL_PCIEPHYRX_DIGITAL_MODES_REG1_MEM_OVRD_PWM_RATE_SHIFT  (6U)
#define CSL_PCIEPHYRX_DIGITAL_MODES_REG1_MEM_OVRD_PWM_RATE_RESETVAL  (0x00000000U)
#define CSL_PCIEPHYRX_DIGITAL_MODES_REG1_MEM_OVRD_PWM_RATE_MAX  (0x00000001U)

#define CSL_PCIEPHYRX_DIGITAL_MODES_REG1_MEM_SPAREBITS_GANGARX_DIGITAL_MODES_REG1_MASK  (0x0000003FU)
#define CSL_PCIEPHYRX_DIGITAL_MODES_REG1_MEM_SPAREBITS_GANGARX_DIGITAL_MODES_REG1_SHIFT  (0U)
#define CSL_PCIEPHYRX_DIGITAL_MODES_REG1_MEM_SPAREBITS_GANGARX_DIGITAL_MODES_REG1_RESETVAL  (0x00000000U)
#define CSL_PCIEPHYRX_DIGITAL_MODES_REG1_MEM_SPAREBITS_GANGARX_DIGITAL_MODES_REG1_MAX  (0x0000003fU)

#define CSL_PCIEPHYRX_DIGITAL_MODES_REG1_RESETVAL               (0x02e33000U)

/* SAMPLER_OFFSET_REG1 */

#define CSL_PCIEPHYRX_SAMPLER_OFFSET_REG1_SAOC_ODD_RD_MASK      (0xFF000000U)
#define CSL_PCIEPHYRX_SAMPLER_OFFSET_REG1_SAOC_ODD_RD_SHIFT     (24U)
#define CSL_PCIEPHYRX_SAMPLER_OFFSET_REG1_SAOC_ODD_RD_RESETVAL  (0x00000000U)
#define CSL_PCIEPHYRX_SAMPLER_OFFSET_REG1_SAOC_ODD_RD_MAX       (0x000000ffU)

#define CSL_PCIEPHYRX_SAMPLER_OFFSET_REG1_SAOC_OETR_RD_MASK     (0x00FF0000U)
#define CSL_PCIEPHYRX_SAMPLER_OFFSET_REG1_SAOC_OETR_RD_SHIFT    (16U)
#define CSL_PCIEPHYRX_SAMPLER_OFFSET_REG1_SAOC_OETR_RD_RESETVAL  (0x00000000U)
#define CSL_PCIEPHYRX_SAMPLER_OFFSET_REG1_SAOC_OETR_RD_MAX      (0x000000ffU)

#define CSL_PCIEPHYRX_SAMPLER_OFFSET_REG1_SAOC_EVEN_RD_MASK     (0x0000FF00U)
#define CSL_PCIEPHYRX_SAMPLER_OFFSET_REG1_SAOC_EVEN_RD_SHIFT    (8U)
#define CSL_PCIEPHYRX_SAMPLER_OFFSET_REG1_SAOC_EVEN_RD_RESETVAL  (0x00000000U)
#define CSL_PCIEPHYRX_SAMPLER_OFFSET_REG1_SAOC_EVEN_RD_MAX      (0x000000ffU)

#define CSL_PCIEPHYRX_SAMPLER_OFFSET_REG1_SAOC_EOTR_RD_MASK     (0x000000FFU)
#define CSL_PCIEPHYRX_SAMPLER_OFFSET_REG1_SAOC_EOTR_RD_SHIFT    (0U)
#define CSL_PCIEPHYRX_SAMPLER_OFFSET_REG1_SAOC_EOTR_RD_RESETVAL  (0x00000000U)
#define CSL_PCIEPHYRX_SAMPLER_OFFSET_REG1_SAOC_EOTR_RD_MAX      (0x000000ffU)

#define CSL_PCIEPHYRX_SAMPLER_OFFSET_REG1_RESETVAL              (0x00000000U)

/* SAMPLER_OFFSET_REG2 */

#define CSL_PCIEPHYRX_SAMPLER_OFFSET_REG2_MEM_SAOC_ODD_VAL_MASK  (0xFF000000U)
#define CSL_PCIEPHYRX_SAMPLER_OFFSET_REG2_MEM_SAOC_ODD_VAL_SHIFT  (24U)
#define CSL_PCIEPHYRX_SAMPLER_OFFSET_REG2_MEM_SAOC_ODD_VAL_RESETVAL  (0x00000000U)
#define CSL_PCIEPHYRX_SAMPLER_OFFSET_REG2_MEM_SAOC_ODD_VAL_MAX  (0x000000ffU)

#define CSL_PCIEPHYRX_SAMPLER_OFFSET_REG2_MEM_SAOC_OETR_VAL_MASK  (0x00FF0000U)
#define CSL_PCIEPHYRX_SAMPLER_OFFSET_REG2_MEM_SAOC_OETR_VAL_SHIFT  (16U)
#define CSL_PCIEPHYRX_SAMPLER_OFFSET_REG2_MEM_SAOC_OETR_VAL_RESETVAL  (0x00000000U)
#define CSL_PCIEPHYRX_SAMPLER_OFFSET_REG2_MEM_SAOC_OETR_VAL_MAX  (0x000000ffU)

#define CSL_PCIEPHYRX_SAMPLER_OFFSET_REG2_MEM_SAOC_EVEN_VAL_MASK  (0x0000FF00U)
#define CSL_PCIEPHYRX_SAMPLER_OFFSET_REG2_MEM_SAOC_EVEN_VAL_SHIFT  (8U)
#define CSL_PCIEPHYRX_SAMPLER_OFFSET_REG2_MEM_SAOC_EVEN_VAL_RESETVAL  (0x00000000U)
#define CSL_PCIEPHYRX_SAMPLER_OFFSET_REG2_MEM_SAOC_EVEN_VAL_MAX  (0x000000ffU)

#define CSL_PCIEPHYRX_SAMPLER_OFFSET_REG2_MEM_SAOC_EOTR_VAL_MASK  (0x000000FFU)
#define CSL_PCIEPHYRX_SAMPLER_OFFSET_REG2_MEM_SAOC_EOTR_VAL_SHIFT  (0U)
#define CSL_PCIEPHYRX_SAMPLER_OFFSET_REG2_MEM_SAOC_EOTR_VAL_RESETVAL  (0x00000000U)
#define CSL_PCIEPHYRX_SAMPLER_OFFSET_REG2_MEM_SAOC_EOTR_VAL_MAX  (0x000000ffU)

#define CSL_PCIEPHYRX_SAMPLER_OFFSET_REG2_RESETVAL              (0x00000000U)

/* SAMPLER_OFFSET_REG3 */

#define CSL_PCIEPHYRX_SAMPLER_OFFSET_REG3_MEM_OVRD_SAOC_ODD_MASK  (0x80000000U)
#define CSL_PCIEPHYRX_SAMPLER_OFFSET_REG3_MEM_OVRD_SAOC_ODD_SHIFT  (31U)
#define CSL_PCIEPHYRX_SAMPLER_OFFSET_REG3_MEM_OVRD_SAOC_ODD_RESETVAL  (0x00000000U)
#define CSL_PCIEPHYRX_SAMPLER_OFFSET_REG3_MEM_OVRD_SAOC_ODD_MAX  (0x00000001U)

#define CSL_PCIEPHYRX_SAMPLER_OFFSET_REG3_MEM_OVRD_SAOC_OETR_MASK  (0x40000000U)
#define CSL_PCIEPHYRX_SAMPLER_OFFSET_REG3_MEM_OVRD_SAOC_OETR_SHIFT  (30U)
#define CSL_PCIEPHYRX_SAMPLER_OFFSET_REG3_MEM_OVRD_SAOC_OETR_RESETVAL  (0x00000000U)
#define CSL_PCIEPHYRX_SAMPLER_OFFSET_REG3_MEM_OVRD_SAOC_OETR_MAX  (0x00000001U)

#define CSL_PCIEPHYRX_SAMPLER_OFFSET_REG3_MEM_OVRD_SAOC_EVEN_MASK  (0x20000000U)
#define CSL_PCIEPHYRX_SAMPLER_OFFSET_REG3_MEM_OVRD_SAOC_EVEN_SHIFT  (29U)
#define CSL_PCIEPHYRX_SAMPLER_OFFSET_REG3_MEM_OVRD_SAOC_EVEN_RESETVAL  (0x00000000U)
#define CSL_PCIEPHYRX_SAMPLER_OFFSET_REG3_MEM_OVRD_SAOC_EVEN_MAX  (0x00000001U)

#define CSL_PCIEPHYRX_SAMPLER_OFFSET_REG3_MEM_OVRD_SAOC_EOTR_MASK  (0x10000000U)
#define CSL_PCIEPHYRX_SAMPLER_OFFSET_REG3_MEM_OVRD_SAOC_EOTR_SHIFT  (28U)
#define CSL_PCIEPHYRX_SAMPLER_OFFSET_REG3_MEM_OVRD_SAOC_EOTR_RESETVAL  (0x00000000U)
#define CSL_PCIEPHYRX_SAMPLER_OFFSET_REG3_MEM_OVRD_SAOC_EOTR_MAX  (0x00000001U)

#define CSL_PCIEPHYRX_SAMPLER_OFFSET_REG3_MEM_SAOC_STL_MASK     (0x0FF00000U)
#define CSL_PCIEPHYRX_SAMPLER_OFFSET_REG3_MEM_SAOC_STL_SHIFT    (20U)
#define CSL_PCIEPHYRX_SAMPLER_OFFSET_REG3_MEM_SAOC_STL_RESETVAL  (0x0000000cU)
#define CSL_PCIEPHYRX_SAMPLER_OFFSET_REG3_MEM_SAOC_STL_MAX      (0x000000ffU)

#define CSL_PCIEPHYRX_SAMPLER_OFFSET_REG3_MEM_SPAREBITS_GANGARX_SAMPLER_OFFSET_REG3_MASK  (0x000FFFFFU)
#define CSL_PCIEPHYRX_SAMPLER_OFFSET_REG3_MEM_SPAREBITS_GANGARX_SAMPLER_OFFSET_REG3_SHIFT  (0U)
#define CSL_PCIEPHYRX_SAMPLER_OFFSET_REG3_MEM_SPAREBITS_GANGARX_SAMPLER_OFFSET_REG3_RESETVAL  (0x00000000U)
#define CSL_PCIEPHYRX_SAMPLER_OFFSET_REG3_MEM_SPAREBITS_GANGARX_SAMPLER_OFFSET_REG3_MAX  (0x000fffffU)

#define CSL_PCIEPHYRX_SAMPLER_OFFSET_REG3_RESETVAL              (0x00c00000U)

/* EQUALIZER_REG1 */

#define CSL_PCIEPHYRX_EQUALIZER_REG1_MEM_EQLEV_MASK             (0xFFFF0000U)
#define CSL_PCIEPHYRX_EQUALIZER_REG1_MEM_EQLEV_SHIFT            (16U)
#define CSL_PCIEPHYRX_EQUALIZER_REG1_MEM_EQLEV_RESETVAL         (0x00000000U)
#define CSL_PCIEPHYRX_EQUALIZER_REG1_MEM_EQLEV_MAX              (0x0000ffffU)

#define CSL_PCIEPHYRX_EQUALIZER_REG1_MEM_EQFTC_MASK             (0x0000F800U)
#define CSL_PCIEPHYRX_EQUALIZER_REG1_MEM_EQFTC_SHIFT            (11U)
#define CSL_PCIEPHYRX_EQUALIZER_REG1_MEM_EQFTC_RESETVAL         (0x00000000U)
#define CSL_PCIEPHYRX_EQUALIZER_REG1_MEM_EQFTC_MAX              (0x0000001fU)

#define CSL_PCIEPHYRX_EQUALIZER_REG1_MEM_EQCTL_MASK             (0x00000780U)
#define CSL_PCIEPHYRX_EQUALIZER_REG1_MEM_EQCTL_SHIFT            (7U)
#define CSL_PCIEPHYRX_EQUALIZER_REG1_MEM_EQCTL_RESETVAL         (0x00000000U)
#define CSL_PCIEPHYRX_EQUALIZER_REG1_MEM_EQCTL_MAX              (0x0000000fU)

#define CSL_PCIEPHYRX_EQUALIZER_REG1_MEM_EQLIMHI_MASK           (0x00000040U)
#define CSL_PCIEPHYRX_EQUALIZER_REG1_MEM_EQLIMHI_SHIFT          (6U)
#define CSL_PCIEPHYRX_EQUALIZER_REG1_MEM_EQLIMHI_RESETVAL       (0x00000000U)
#define CSL_PCIEPHYRX_EQUALIZER_REG1_MEM_EQLIMHI_MAX            (0x00000001U)

#define CSL_PCIEPHYRX_EQUALIZER_REG1_MEM_EQLIMLO_MASK           (0x00000020U)
#define CSL_PCIEPHYRX_EQUALIZER_REG1_MEM_EQLIMLO_SHIFT          (5U)
#define CSL_PCIEPHYRX_EQUALIZER_REG1_MEM_EQLIMLO_RESETVAL       (0x00000000U)
#define CSL_PCIEPHYRX_EQUALIZER_REG1_MEM_EQLIMLO_MAX            (0x00000001U)

#define CSL_PCIEPHYRX_EQUALIZER_REG1_MEM_EQLOCK_MASK            (0x00000010U)
#define CSL_PCIEPHYRX_EQUALIZER_REG1_MEM_EQLOCK_SHIFT           (4U)
#define CSL_PCIEPHYRX_EQUALIZER_REG1_MEM_EQLOCK_RESETVAL        (0x00000000U)
#define CSL_PCIEPHYRX_EQUALIZER_REG1_MEM_EQLOCK_MAX             (0x00000001U)

#define CSL_PCIEPHYRX_EQUALIZER_REG1_MEM_EQSET_MASK             (0x00000008U)
#define CSL_PCIEPHYRX_EQUALIZER_REG1_MEM_EQSET_SHIFT            (3U)
#define CSL_PCIEPHYRX_EQUALIZER_REG1_MEM_EQSET_RESETVAL         (0x00000000U)
#define CSL_PCIEPHYRX_EQUALIZER_REG1_MEM_EQSET_MAX              (0x00000001U)

#define CSL_PCIEPHYRX_EQUALIZER_REG1_MEM_OVRD_EQLEV_MASK        (0x00000004U)
#define CSL_PCIEPHYRX_EQUALIZER_REG1_MEM_OVRD_EQLEV_SHIFT       (2U)
#define CSL_PCIEPHYRX_EQUALIZER_REG1_MEM_OVRD_EQLEV_RESETVAL    (0x00000000U)
#define CSL_PCIEPHYRX_EQUALIZER_REG1_MEM_OVRD_EQLEV_MAX         (0x00000001U)

#define CSL_PCIEPHYRX_EQUALIZER_REG1_MEM_OVRD_EQFTC_MASK        (0x00000002U)
#define CSL_PCIEPHYRX_EQUALIZER_REG1_MEM_OVRD_EQFTC_SHIFT       (1U)
#define CSL_PCIEPHYRX_EQUALIZER_REG1_MEM_OVRD_EQFTC_RESETVAL    (0x00000000U)
#define CSL_PCIEPHYRX_EQUALIZER_REG1_MEM_OVRD_EQFTC_MAX         (0x00000001U)

#define CSL_PCIEPHYRX_EQUALIZER_REG1_MEM_EN_DET_3SYMISI_MASK    (0x00000001U)
#define CSL_PCIEPHYRX_EQUALIZER_REG1_MEM_EN_DET_3SYMISI_SHIFT   (0U)
#define CSL_PCIEPHYRX_EQUALIZER_REG1_MEM_EN_DET_3SYMISI_RESETVAL  (0x00000000U)
#define CSL_PCIEPHYRX_EQUALIZER_REG1_MEM_EN_DET_3SYMISI_MAX     (0x00000001U)

#define CSL_PCIEPHYRX_EQUALIZER_REG1_RESETVAL                   (0x00000000U)

/* EQUALIZER_REG2 */

#define CSL_PCIEPHYRX_EQUALIZER_REG2_EQLEV_RD_MASK              (0xFFFF0000U)
#define CSL_PCIEPHYRX_EQUALIZER_REG2_EQLEV_RD_SHIFT             (16U)
#define CSL_PCIEPHYRX_EQUALIZER_REG2_EQLEV_RD_RESETVAL          (0x000000ffU)
#define CSL_PCIEPHYRX_EQUALIZER_REG2_EQLEV_RD_MAX               (0x0000ffffU)

#define CSL_PCIEPHYRX_EQUALIZER_REG2_EQFTC_RD_MASK              (0x0000F800U)
#define CSL_PCIEPHYRX_EQUALIZER_REG2_EQFTC_RD_SHIFT             (11U)
#define CSL_PCIEPHYRX_EQUALIZER_REG2_EQFTC_RD_RESETVAL          (0x0000001eU)
#define CSL_PCIEPHYRX_EQUALIZER_REG2_EQFTC_RD_MAX               (0x0000001fU)

#define CSL_PCIEPHYRX_EQUALIZER_REG2_SPAREBITS_GANGARX_EQUALIZER_REG2_MASK  (0x000007FFU)
#define CSL_PCIEPHYRX_EQUALIZER_REG2_SPAREBITS_GANGARX_EQUALIZER_REG2_SHIFT  (0U)
#define CSL_PCIEPHYRX_EQUALIZER_REG2_SPAREBITS_GANGARX_EQUALIZER_REG2_RESETVAL  (0x00000000U)
#define CSL_PCIEPHYRX_EQUALIZER_REG2_SPAREBITS_GANGARX_EQUALIZER_REG2_MAX  (0x000007ffU)

#define CSL_PCIEPHYRX_EQUALIZER_REG2_RESETVAL                   (0x00fff000U)

/* EYESCAN_REG1 */

#define CSL_PCIEPHYRX_EYESCAN_REG1_MEM_ES_MODE_MASK             (0xC0000000U)
#define CSL_PCIEPHYRX_EYESCAN_REG1_MEM_ES_MODE_SHIFT            (30U)
#define CSL_PCIEPHYRX_EYESCAN_REG1_MEM_ES_MODE_RESETVAL         (0x00000000U)
#define CSL_PCIEPHYRX_EYESCAN_REG1_MEM_ES_MODE_MAX              (0x00000003U)

#define CSL_PCIEPHYRX_EYESCAN_REG1_MEM_ES_PHOFF_MASK            (0x3FC00000U)
#define CSL_PCIEPHYRX_EYESCAN_REG1_MEM_ES_PHOFF_SHIFT           (22U)
#define CSL_PCIEPHYRX_EYESCAN_REG1_MEM_ES_PHOFF_RESETVAL        (0x00000000U)
#define CSL_PCIEPHYRX_EYESCAN_REG1_MEM_ES_PHOFF_MAX             (0x000000ffU)

#define CSL_PCIEPHYRX_EYESCAN_REG1_MEM_ES_VOFF_MASK             (0x003FC000U)
#define CSL_PCIEPHYRX_EYESCAN_REG1_MEM_ES_VOFF_SHIFT            (14U)
#define CSL_PCIEPHYRX_EYESCAN_REG1_MEM_ES_VOFF_RESETVAL         (0x00000000U)
#define CSL_PCIEPHYRX_EYESCAN_REG1_MEM_ES_VOFF_MAX              (0x000000ffU)

#define CSL_PCIEPHYRX_EYESCAN_REG1_MEM_ES_MSR_INTRVL_MASK       (0x00003000U)
#define CSL_PCIEPHYRX_EYESCAN_REG1_MEM_ES_MSR_INTRVL_SHIFT      (12U)
#define CSL_PCIEPHYRX_EYESCAN_REG1_MEM_ES_MSR_INTRVL_RESETVAL   (0x00000002U)
#define CSL_PCIEPHYRX_EYESCAN_REG1_MEM_ES_MSR_INTRVL_MAX        (0x00000003U)

#define CSL_PCIEPHYRX_EYESCAN_REG1_MEM_ES_FORCEFREQOFF_MASK     (0x00000800U)
#define CSL_PCIEPHYRX_EYESCAN_REG1_MEM_ES_FORCEFREQOFF_SHIFT    (11U)
#define CSL_PCIEPHYRX_EYESCAN_REG1_MEM_ES_FORCEFREQOFF_RESETVAL  (0x00000000U)
#define CSL_PCIEPHYRX_EYESCAN_REG1_MEM_ES_FORCEFREQOFF_MAX      (0x00000001U)

#define CSL_PCIEPHYRX_EYESCAN_REG1_MEM_ES_FREQOFF_MASK          (0x000007FFU)
#define CSL_PCIEPHYRX_EYESCAN_REG1_MEM_ES_FREQOFF_SHIFT         (0U)
#define CSL_PCIEPHYRX_EYESCAN_REG1_MEM_ES_FREQOFF_RESETVAL      (0x00000000U)
#define CSL_PCIEPHYRX_EYESCAN_REG1_MEM_ES_FREQOFF_MAX           (0x000007ffU)

#define CSL_PCIEPHYRX_EYESCAN_REG1_RESETVAL                     (0x00002000U)

/* IO_AND_A2D_OVERRIDES_REG1 */

#define CSL_PCIEPHYRX_IO_AND_A2D_OVERRIDES_REG1_MEM_OVRD_RD_MASK  (0x80000000U)
#define CSL_PCIEPHYRX_IO_AND_A2D_OVERRIDES_REG1_MEM_OVRD_RD_SHIFT  (31U)
#define CSL_PCIEPHYRX_IO_AND_A2D_OVERRIDES_REG1_MEM_OVRD_RD_RESETVAL  (0x00000000U)
#define CSL_PCIEPHYRX_IO_AND_A2D_OVERRIDES_REG1_MEM_OVRD_RD_MAX  (0x00000001U)

#define CSL_PCIEPHYRX_IO_AND_A2D_OVERRIDES_REG1_MEM_RD_VAL_MASK  (0x7FE00000U)
#define CSL_PCIEPHYRX_IO_AND_A2D_OVERRIDES_REG1_MEM_RD_VAL_SHIFT  (21U)
#define CSL_PCIEPHYRX_IO_AND_A2D_OVERRIDES_REG1_MEM_RD_VAL_RESETVAL  (0x00000000U)
#define CSL_PCIEPHYRX_IO_AND_A2D_OVERRIDES_REG1_MEM_RD_VAL_MAX  (0x000003ffU)

#define CSL_PCIEPHYRX_IO_AND_A2D_OVERRIDES_REG1_MEM_OVRD_ODDCG_MASK  (0x00100000U)
#define CSL_PCIEPHYRX_IO_AND_A2D_OVERRIDES_REG1_MEM_OVRD_ODDCG_SHIFT  (20U)
#define CSL_PCIEPHYRX_IO_AND_A2D_OVERRIDES_REG1_MEM_OVRD_ODDCG_RESETVAL  (0x00000000U)
#define CSL_PCIEPHYRX_IO_AND_A2D_OVERRIDES_REG1_MEM_OVRD_ODDCG_MAX  (0x00000001U)

#define CSL_PCIEPHYRX_IO_AND_A2D_OVERRIDES_REG1_MEM_ODDCG_VAL_MASK  (0x00080000U)
#define CSL_PCIEPHYRX_IO_AND_A2D_OVERRIDES_REG1_MEM_ODDCG_VAL_SHIFT  (19U)
#define CSL_PCIEPHYRX_IO_AND_A2D_OVERRIDES_REG1_MEM_ODDCG_VAL_RESETVAL  (0x00000000U)
#define CSL_PCIEPHYRX_IO_AND_A2D_OVERRIDES_REG1_MEM_ODDCG_VAL_MAX  (0x00000001U)

#define CSL_PCIEPHYRX_IO_AND_A2D_OVERRIDES_REG1_MEM_OVRD_SYNC_MASK  (0x00040000U)
#define CSL_PCIEPHYRX_IO_AND_A2D_OVERRIDES_REG1_MEM_OVRD_SYNC_SHIFT  (18U)
#define CSL_PCIEPHYRX_IO_AND_A2D_OVERRIDES_REG1_MEM_OVRD_SYNC_RESETVAL  (0x00000000U)
#define CSL_PCIEPHYRX_IO_AND_A2D_OVERRIDES_REG1_MEM_OVRD_SYNC_MAX  (0x00000001U)

#define CSL_PCIEPHYRX_IO_AND_A2D_OVERRIDES_REG1_MEM_SYNC_VAL_MASK  (0x00020000U)
#define CSL_PCIEPHYRX_IO_AND_A2D_OVERRIDES_REG1_MEM_SYNC_VAL_SHIFT  (17U)
#define CSL_PCIEPHYRX_IO_AND_A2D_OVERRIDES_REG1_MEM_SYNC_VAL_RESETVAL  (0x00000000U)
#define CSL_PCIEPHYRX_IO_AND_A2D_OVERRIDES_REG1_MEM_SYNC_VAL_MAX  (0x00000001U)

#define CSL_PCIEPHYRX_IO_AND_A2D_OVERRIDES_REG1_MEM_OVRD_ERRSYNC_MASK  (0x00010000U)
#define CSL_PCIEPHYRX_IO_AND_A2D_OVERRIDES_REG1_MEM_OVRD_ERRSYNC_SHIFT  (16U)
#define CSL_PCIEPHYRX_IO_AND_A2D_OVERRIDES_REG1_MEM_OVRD_ERRSYNC_RESETVAL  (0x00000000U)
#define CSL_PCIEPHYRX_IO_AND_A2D_OVERRIDES_REG1_MEM_OVRD_ERRSYNC_MAX  (0x00000001U)

#define CSL_PCIEPHYRX_IO_AND_A2D_OVERRIDES_REG1_MEM_ERRSYNC_VAL_MASK  (0x00008000U)
#define CSL_PCIEPHYRX_IO_AND_A2D_OVERRIDES_REG1_MEM_ERRSYNC_VAL_SHIFT  (15U)
#define CSL_PCIEPHYRX_IO_AND_A2D_OVERRIDES_REG1_MEM_ERRSYNC_VAL_RESETVAL  (0x00000000U)
#define CSL_PCIEPHYRX_IO_AND_A2D_OVERRIDES_REG1_MEM_ERRSYNC_VAL_MAX  (0x00000001U)

#define CSL_PCIEPHYRX_IO_AND_A2D_OVERRIDES_REG1_MEM_OVRD_LOS_STS_MASK  (0x00004000U)
#define CSL_PCIEPHYRX_IO_AND_A2D_OVERRIDES_REG1_MEM_OVRD_LOS_STS_SHIFT  (14U)
#define CSL_PCIEPHYRX_IO_AND_A2D_OVERRIDES_REG1_MEM_OVRD_LOS_STS_RESETVAL  (0x00000000U)
#define CSL_PCIEPHYRX_IO_AND_A2D_OVERRIDES_REG1_MEM_OVRD_LOS_STS_MAX  (0x00000001U)

#define CSL_PCIEPHYRX_IO_AND_A2D_OVERRIDES_REG1_MEM_LOS_STS_VAL_MASK  (0x00002000U)
#define CSL_PCIEPHYRX_IO_AND_A2D_OVERRIDES_REG1_MEM_LOS_STS_VAL_SHIFT  (13U)
#define CSL_PCIEPHYRX_IO_AND_A2D_OVERRIDES_REG1_MEM_LOS_STS_VAL_RESETVAL  (0x00000000U)
#define CSL_PCIEPHYRX_IO_AND_A2D_OVERRIDES_REG1_MEM_LOS_STS_VAL_MAX  (0x00000001U)

#define CSL_PCIEPHYRX_IO_AND_A2D_OVERRIDES_REG1_MEM_OVRD_JOGREQ_MASK  (0x00001000U)
#define CSL_PCIEPHYRX_IO_AND_A2D_OVERRIDES_REG1_MEM_OVRD_JOGREQ_SHIFT  (12U)
#define CSL_PCIEPHYRX_IO_AND_A2D_OVERRIDES_REG1_MEM_OVRD_JOGREQ_RESETVAL  (0x00000000U)
#define CSL_PCIEPHYRX_IO_AND_A2D_OVERRIDES_REG1_MEM_OVRD_JOGREQ_MAX  (0x00000001U)

#define CSL_PCIEPHYRX_IO_AND_A2D_OVERRIDES_REG1_MEM_JOGREQ_VAL_MASK  (0x00000800U)
#define CSL_PCIEPHYRX_IO_AND_A2D_OVERRIDES_REG1_MEM_JOGREQ_VAL_SHIFT  (11U)
#define CSL_PCIEPHYRX_IO_AND_A2D_OVERRIDES_REG1_MEM_JOGREQ_VAL_RESETVAL  (0x00000000U)
#define CSL_PCIEPHYRX_IO_AND_A2D_OVERRIDES_REG1_MEM_JOGREQ_VAL_MAX  (0x00000001U)

#define CSL_PCIEPHYRX_IO_AND_A2D_OVERRIDES_REG1_MEM_CDR_LOS_SOURCE_MASK  (0x00000600U)
#define CSL_PCIEPHYRX_IO_AND_A2D_OVERRIDES_REG1_MEM_CDR_LOS_SOURCE_SHIFT  (9U)
#define CSL_PCIEPHYRX_IO_AND_A2D_OVERRIDES_REG1_MEM_CDR_LOS_SOURCE_RESETVAL  (0x00000001U)
#define CSL_PCIEPHYRX_IO_AND_A2D_OVERRIDES_REG1_MEM_CDR_LOS_SOURCE_MAX  (0x00000003U)

#define CSL_PCIEPHYRX_IO_AND_A2D_OVERRIDES_REG1_MEM_LOS_TO_CDR_VAL_MASK  (0x00000100U)
#define CSL_PCIEPHYRX_IO_AND_A2D_OVERRIDES_REG1_MEM_LOS_TO_CDR_VAL_SHIFT  (8U)
#define CSL_PCIEPHYRX_IO_AND_A2D_OVERRIDES_REG1_MEM_LOS_TO_CDR_VAL_RESETVAL  (0x00000000U)
#define CSL_PCIEPHYRX_IO_AND_A2D_OVERRIDES_REG1_MEM_LOS_TO_CDR_VAL_MAX  (0x00000001U)

#define CSL_PCIEPHYRX_IO_AND_A2D_OVERRIDES_REG1_MEM_OVRD_LSDATAOUT_MASK  (0x00000080U)
#define CSL_PCIEPHYRX_IO_AND_A2D_OVERRIDES_REG1_MEM_OVRD_LSDATAOUT_SHIFT  (7U)
#define CSL_PCIEPHYRX_IO_AND_A2D_OVERRIDES_REG1_MEM_OVRD_LSDATAOUT_RESETVAL  (0x00000000U)
#define CSL_PCIEPHYRX_IO_AND_A2D_OVERRIDES_REG1_MEM_OVRD_LSDATAOUT_MAX  (0x00000001U)

#define CSL_PCIEPHYRX_IO_AND_A2D_OVERRIDES_REG1_MEM_LSDATAOUT_VAL_MASK  (0x00000040U)
#define CSL_PCIEPHYRX_IO_AND_A2D_OVERRIDES_REG1_MEM_LSDATAOUT_VAL_SHIFT  (6U)
#define CSL_PCIEPHYRX_IO_AND_A2D_OVERRIDES_REG1_MEM_LSDATAOUT_VAL_RESETVAL  (0x00000000U)
#define CSL_PCIEPHYRX_IO_AND_A2D_OVERRIDES_REG1_MEM_LSDATAOUT_VAL_MAX  (0x00000001U)

#define CSL_PCIEPHYRX_IO_AND_A2D_OVERRIDES_REG1_MEM_SPAREBITS_GANGARX_IO_AND_A2D_OVERRIDES_REG1_MASK  (0x0000003FU)
#define CSL_PCIEPHYRX_IO_AND_A2D_OVERRIDES_REG1_MEM_SPAREBITS_GANGARX_IO_AND_A2D_OVERRIDES_REG1_SHIFT  (0U)
#define CSL_PCIEPHYRX_IO_AND_A2D_OVERRIDES_REG1_MEM_SPAREBITS_GANGARX_IO_AND_A2D_OVERRIDES_REG1_RESETVAL  (0x00000000U)
#define CSL_PCIEPHYRX_IO_AND_A2D_OVERRIDES_REG1_MEM_SPAREBITS_GANGARX_IO_AND_A2D_OVERRIDES_REG1_MAX  (0x0000003fU)

#define CSL_PCIEPHYRX_IO_AND_A2D_OVERRIDES_REG1_RESETVAL        (0x00000200U)

/* IO_AND_A2D_OVERRIDES_REG2 */

#define CSL_PCIEPHYRX_IO_AND_A2D_OVERRIDES_REG2_MEM_OVRD_RXA_FORCE_0DIFF_MASK  (0x80000000U)
#define CSL_PCIEPHYRX_IO_AND_A2D_OVERRIDES_REG2_MEM_OVRD_RXA_FORCE_0DIFF_SHIFT  (31U)
#define CSL_PCIEPHYRX_IO_AND_A2D_OVERRIDES_REG2_MEM_OVRD_RXA_FORCE_0DIFF_RESETVAL  (0x00000000U)
#define CSL_PCIEPHYRX_IO_AND_A2D_OVERRIDES_REG2_MEM_OVRD_RXA_FORCE_0DIFF_MAX  (0x00000001U)

#define CSL_PCIEPHYRX_IO_AND_A2D_OVERRIDES_REG2_MEM_RXA_FORCE_0DIFF_VAL_MASK  (0x40000000U)
#define CSL_PCIEPHYRX_IO_AND_A2D_OVERRIDES_REG2_MEM_RXA_FORCE_0DIFF_VAL_SHIFT  (30U)
#define CSL_PCIEPHYRX_IO_AND_A2D_OVERRIDES_REG2_MEM_RXA_FORCE_0DIFF_VAL_RESETVAL  (0x00000000U)
#define CSL_PCIEPHYRX_IO_AND_A2D_OVERRIDES_REG2_MEM_RXA_FORCE_0DIFF_VAL_MAX  (0x00000001U)

#define CSL_PCIEPHYRX_IO_AND_A2D_OVERRIDES_REG2_MEM_OVRD_EN_DLLOFFSETCAL_MASK  (0x20000000U)
#define CSL_PCIEPHYRX_IO_AND_A2D_OVERRIDES_REG2_MEM_OVRD_EN_DLLOFFSETCAL_SHIFT  (29U)
#define CSL_PCIEPHYRX_IO_AND_A2D_OVERRIDES_REG2_MEM_OVRD_EN_DLLOFFSETCAL_RESETVAL  (0x00000000U)
#define CSL_PCIEPHYRX_IO_AND_A2D_OVERRIDES_REG2_MEM_OVRD_EN_DLLOFFSETCAL_MAX  (0x00000001U)

#define CSL_PCIEPHYRX_IO_AND_A2D_OVERRIDES_REG2_MEM_EN_DLLOFFSETCAL_VAL_MASK  (0x10000000U)
#define CSL_PCIEPHYRX_IO_AND_A2D_OVERRIDES_REG2_MEM_EN_DLLOFFSETCAL_VAL_SHIFT  (28U)
#define CSL_PCIEPHYRX_IO_AND_A2D_OVERRIDES_REG2_MEM_EN_DLLOFFSETCAL_VAL_RESETVAL  (0x00000000U)
#define CSL_PCIEPHYRX_IO_AND_A2D_OVERRIDES_REG2_MEM_EN_DLLOFFSETCAL_VAL_MAX  (0x00000001U)

#define CSL_PCIEPHYRX_IO_AND_A2D_OVERRIDES_REG2_MEM_OVRD_EN_DLLCOARSECAL_MASK  (0x08000000U)
#define CSL_PCIEPHYRX_IO_AND_A2D_OVERRIDES_REG2_MEM_OVRD_EN_DLLCOARSECAL_SHIFT  (27U)
#define CSL_PCIEPHYRX_IO_AND_A2D_OVERRIDES_REG2_MEM_OVRD_EN_DLLCOARSECAL_RESETVAL  (0x00000000U)
#define CSL_PCIEPHYRX_IO_AND_A2D_OVERRIDES_REG2_MEM_OVRD_EN_DLLCOARSECAL_MAX  (0x00000001U)

#define CSL_PCIEPHYRX_IO_AND_A2D_OVERRIDES_REG2_MEM_EN_DLLCOARSECAL_VAL_MASK  (0x06000000U)
#define CSL_PCIEPHYRX_IO_AND_A2D_OVERRIDES_REG2_MEM_EN_DLLCOARSECAL_VAL_SHIFT  (25U)
#define CSL_PCIEPHYRX_IO_AND_A2D_OVERRIDES_REG2_MEM_EN_DLLCOARSECAL_VAL_RESETVAL  (0x00000000U)
#define CSL_PCIEPHYRX_IO_AND_A2D_OVERRIDES_REG2_MEM_EN_DLLCOARSECAL_VAL_MAX  (0x00000003U)

#define CSL_PCIEPHYRX_IO_AND_A2D_OVERRIDES_REG2_MEM_OVRD_POWER_CTRL_IN_MASK  (0x01000000U)
#define CSL_PCIEPHYRX_IO_AND_A2D_OVERRIDES_REG2_MEM_OVRD_POWER_CTRL_IN_SHIFT  (24U)
#define CSL_PCIEPHYRX_IO_AND_A2D_OVERRIDES_REG2_MEM_OVRD_POWER_CTRL_IN_RESETVAL  (0x00000000U)
#define CSL_PCIEPHYRX_IO_AND_A2D_OVERRIDES_REG2_MEM_OVRD_POWER_CTRL_IN_MAX  (0x00000001U)

#define CSL_PCIEPHYRX_IO_AND_A2D_OVERRIDES_REG2_MEM_POWER_CTRL_IN_VAL_MASK  (0x00FC0000U)
#define CSL_PCIEPHYRX_IO_AND_A2D_OVERRIDES_REG2_MEM_POWER_CTRL_IN_VAL_SHIFT  (18U)
#define CSL_PCIEPHYRX_IO_AND_A2D_OVERRIDES_REG2_MEM_POWER_CTRL_IN_VAL_RESETVAL  (0x00000000U)
#define CSL_PCIEPHYRX_IO_AND_A2D_OVERRIDES_REG2_MEM_POWER_CTRL_IN_VAL_MAX  (0x0000003fU)

#define CSL_PCIEPHYRX_IO_AND_A2D_OVERRIDES_REG2_MEM_SPAREBITS_GANGARX_IO_AND_A2D_OVERRIDES_REG2_MASK  (0x0003FFFFU)
#define CSL_PCIEPHYRX_IO_AND_A2D_OVERRIDES_REG2_MEM_SPAREBITS_GANGARX_IO_AND_A2D_OVERRIDES_REG2_SHIFT  (0U)
#define CSL_PCIEPHYRX_IO_AND_A2D_OVERRIDES_REG2_MEM_SPAREBITS_GANGARX_IO_AND_A2D_OVERRIDES_REG2_RESETVAL  (0x00000000U)
#define CSL_PCIEPHYRX_IO_AND_A2D_OVERRIDES_REG2_MEM_SPAREBITS_GANGARX_IO_AND_A2D_OVERRIDES_REG2_MAX  (0x0003ffffU)

#define CSL_PCIEPHYRX_IO_AND_A2D_OVERRIDES_REG2_RESETVAL        (0x00000000U)

/* TESTABILITY_CTRL_REG1 */

#define CSL_PCIEPHYRX_TESTABILITY_CTRL_REG1_MEM_UPDATE_SHADOW_OF_ES_BERT_MASK  (0x80000000U)
#define CSL_PCIEPHYRX_TESTABILITY_CTRL_REG1_MEM_UPDATE_SHADOW_OF_ES_BERT_SHIFT  (31U)
#define CSL_PCIEPHYRX_TESTABILITY_CTRL_REG1_MEM_UPDATE_SHADOW_OF_ES_BERT_RESETVAL  (0x00000000U)
#define CSL_PCIEPHYRX_TESTABILITY_CTRL_REG1_MEM_UPDATE_SHADOW_OF_ES_BERT_MAX  (0x00000001U)

#define CSL_PCIEPHYRX_TESTABILITY_CTRL_REG1_MEM_EN_ES_MASK      (0x40000000U)
#define CSL_PCIEPHYRX_TESTABILITY_CTRL_REG1_MEM_EN_ES_SHIFT     (30U)
#define CSL_PCIEPHYRX_TESTABILITY_CTRL_REG1_MEM_EN_ES_RESETVAL  (0x00000000U)
#define CSL_PCIEPHYRX_TESTABILITY_CTRL_REG1_MEM_EN_ES_MAX       (0x00000001U)

#define CSL_PCIEPHYRX_TESTABILITY_CTRL_REG1_MEM_EN_PV_MASK      (0x20000000U)
#define CSL_PCIEPHYRX_TESTABILITY_CTRL_REG1_MEM_EN_PV_SHIFT     (29U)
#define CSL_PCIEPHYRX_TESTABILITY_CTRL_REG1_MEM_EN_PV_RESETVAL  (0x00000000U)
#define CSL_PCIEPHYRX_TESTABILITY_CTRL_REG1_MEM_EN_PV_MAX       (0x00000001U)

#define CSL_PCIEPHYRX_TESTABILITY_CTRL_REG1_MEM_PV_PATT_MASK    (0x18000000U)
#define CSL_PCIEPHYRX_TESTABILITY_CTRL_REG1_MEM_PV_PATT_SHIFT   (27U)
#define CSL_PCIEPHYRX_TESTABILITY_CTRL_REG1_MEM_PV_PATT_RESETVAL  (0x00000000U)
#define CSL_PCIEPHYRX_TESTABILITY_CTRL_REG1_MEM_PV_PATT_MAX     (0x00000003U)

#define CSL_PCIEPHYRX_TESTABILITY_CTRL_REG1_MEM_EN_ALT_LPBK_MASK  (0x04000000U)
#define CSL_PCIEPHYRX_TESTABILITY_CTRL_REG1_MEM_EN_ALT_LPBK_SHIFT  (26U)
#define CSL_PCIEPHYRX_TESTABILITY_CTRL_REG1_MEM_EN_ALT_LPBK_RESETVAL  (0x00000000U)
#define CSL_PCIEPHYRX_TESTABILITY_CTRL_REG1_MEM_EN_ALT_LPBK_MAX  (0x00000001U)

#define CSL_PCIEPHYRX_TESTABILITY_CTRL_REG1_MEM_EN_DIG_LPBK_MASK  (0x02000000U)
#define CSL_PCIEPHYRX_TESTABILITY_CTRL_REG1_MEM_EN_DIG_LPBK_SHIFT  (25U)
#define CSL_PCIEPHYRX_TESTABILITY_CTRL_REG1_MEM_EN_DIG_LPBK_RESETVAL  (0x00000000U)
#define CSL_PCIEPHYRX_TESTABILITY_CTRL_REG1_MEM_EN_DIG_LPBK_MAX  (0x00000001U)

#define CSL_PCIEPHYRX_TESTABILITY_CTRL_REG1_MEM_EN_EXT_VREF_MASK  (0x01000000U)
#define CSL_PCIEPHYRX_TESTABILITY_CTRL_REG1_MEM_EN_EXT_VREF_SHIFT  (24U)
#define CSL_PCIEPHYRX_TESTABILITY_CTRL_REG1_MEM_EN_EXT_VREF_RESETVAL  (0x00000000U)
#define CSL_PCIEPHYRX_TESTABILITY_CTRL_REG1_MEM_EN_EXT_VREF_MAX  (0x00000001U)

#define CSL_PCIEPHYRX_TESTABILITY_CTRL_REG1_MEM_RXASEL_MASK     (0x00E00000U)
#define CSL_PCIEPHYRX_TESTABILITY_CTRL_REG1_MEM_RXASEL_SHIFT    (21U)
#define CSL_PCIEPHYRX_TESTABILITY_CTRL_REG1_MEM_RXASEL_RESETVAL  (0x00000000U)
#define CSL_PCIEPHYRX_TESTABILITY_CTRL_REG1_MEM_RXASEL_MAX      (0x00000007U)

#define CSL_PCIEPHYRX_TESTABILITY_CTRL_REG1_MEM_RXA_ENBS_MASK   (0x00100000U)
#define CSL_PCIEPHYRX_TESTABILITY_CTRL_REG1_MEM_RXA_ENBS_SHIFT  (20U)
#define CSL_PCIEPHYRX_TESTABILITY_CTRL_REG1_MEM_RXA_ENBS_RESETVAL  (0x00000000U)
#define CSL_PCIEPHYRX_TESTABILITY_CTRL_REG1_MEM_RXA_ENBS_MAX    (0x00000001U)

#define CSL_PCIEPHYRX_TESTABILITY_CTRL_REG1_MEM_RXA_ENBSLEV_MASK  (0x00080000U)
#define CSL_PCIEPHYRX_TESTABILITY_CTRL_REG1_MEM_RXA_ENBSLEV_SHIFT  (19U)
#define CSL_PCIEPHYRX_TESTABILITY_CTRL_REG1_MEM_RXA_ENBSLEV_RESETVAL  (0x00000000U)
#define CSL_PCIEPHYRX_TESTABILITY_CTRL_REG1_MEM_RXA_ENBSLEV_MAX  (0x00000001U)

#define CSL_PCIEPHYRX_TESTABILITY_CTRL_REG1_MEM_RXA_BSPSTATE_MASK  (0x00040000U)
#define CSL_PCIEPHYRX_TESTABILITY_CTRL_REG1_MEM_RXA_BSPSTATE_SHIFT  (18U)
#define CSL_PCIEPHYRX_TESTABILITY_CTRL_REG1_MEM_RXA_BSPSTATE_RESETVAL  (0x00000000U)
#define CSL_PCIEPHYRX_TESTABILITY_CTRL_REG1_MEM_RXA_BSPSTATE_MAX  (0x00000001U)

#define CSL_PCIEPHYRX_TESTABILITY_CTRL_REG1_MEM_RXA_BSNSTATE_MASK  (0x00020000U)
#define CSL_PCIEPHYRX_TESTABILITY_CTRL_REG1_MEM_RXA_BSNSTATE_SHIFT  (17U)
#define CSL_PCIEPHYRX_TESTABILITY_CTRL_REG1_MEM_RXA_BSNSTATE_RESETVAL  (0x00000000U)
#define CSL_PCIEPHYRX_TESTABILITY_CTRL_REG1_MEM_RXA_BSNSTATE_MAX  (0x00000001U)

#define CSL_PCIEPHYRX_TESTABILITY_CTRL_REG1_MEM_RXA_BSINIT_MASK  (0x00010000U)
#define CSL_PCIEPHYRX_TESTABILITY_CTRL_REG1_MEM_RXA_BSINIT_SHIFT  (16U)
#define CSL_PCIEPHYRX_TESTABILITY_CTRL_REG1_MEM_RXA_BSINIT_RESETVAL  (0x00000000U)
#define CSL_PCIEPHYRX_TESTABILITY_CTRL_REG1_MEM_RXA_BSINIT_MAX  (0x00000001U)

#define CSL_PCIEPHYRX_TESTABILITY_CTRL_REG1_MEM_SPAREBITS_GANGARX_TESTABILITY_CTRL_REG1_MASK  (0x0000FFFFU)
#define CSL_PCIEPHYRX_TESTABILITY_CTRL_REG1_MEM_SPAREBITS_GANGARX_TESTABILITY_CTRL_REG1_SHIFT  (0U)
#define CSL_PCIEPHYRX_TESTABILITY_CTRL_REG1_MEM_SPAREBITS_GANGARX_TESTABILITY_CTRL_REG1_RESETVAL  (0x00000000U)
#define CSL_PCIEPHYRX_TESTABILITY_CTRL_REG1_MEM_SPAREBITS_GANGARX_TESTABILITY_CTRL_REG1_MAX  (0x0000ffffU)

#define CSL_PCIEPHYRX_TESTABILITY_CTRL_REG1_RESETVAL            (0x00000000U)

/* OBSERVE_REG1 */

#define CSL_PCIEPHYRX_OBSERVE_REG1_RD_MASK                      (0xFFC00000U)
#define CSL_PCIEPHYRX_OBSERVE_REG1_RD_SHIFT                     (22U)
#define CSL_PCIEPHYRX_OBSERVE_REG1_RD_RESETVAL                  (0x00000000U)
#define CSL_PCIEPHYRX_OBSERVE_REG1_RD_MAX                       (0x000003ffU)

#define CSL_PCIEPHYRX_OBSERVE_REG1_ODDCG_RD_MASK                (0x00200000U)
#define CSL_PCIEPHYRX_OBSERVE_REG1_ODDCG_RD_SHIFT               (21U)
#define CSL_PCIEPHYRX_OBSERVE_REG1_ODDCG_RD_RESETVAL            (0x00000000U)
#define CSL_PCIEPHYRX_OBSERVE_REG1_ODDCG_RD_MAX                 (0x00000001U)

#define CSL_PCIEPHYRX_OBSERVE_REG1_SYNC_RD_MASK                 (0x00100000U)
#define CSL_PCIEPHYRX_OBSERVE_REG1_SYNC_RD_SHIFT                (20U)
#define CSL_PCIEPHYRX_OBSERVE_REG1_SYNC_RD_RESETVAL             (0x00000000U)
#define CSL_PCIEPHYRX_OBSERVE_REG1_SYNC_RD_MAX                  (0x00000001U)

#define CSL_PCIEPHYRX_OBSERVE_REG1_ERRSYNC_RD_MASK              (0x00080000U)
#define CSL_PCIEPHYRX_OBSERVE_REG1_ERRSYNC_RD_SHIFT             (19U)
#define CSL_PCIEPHYRX_OBSERVE_REG1_ERRSYNC_RD_RESETVAL          (0x00000000U)
#define CSL_PCIEPHYRX_OBSERVE_REG1_ERRSYNC_RD_MAX               (0x00000001U)

#define CSL_PCIEPHYRX_OBSERVE_REG1_LOS_STS_RD_MASK              (0x00040000U)
#define CSL_PCIEPHYRX_OBSERVE_REG1_LOS_STS_RD_SHIFT             (18U)
#define CSL_PCIEPHYRX_OBSERVE_REG1_LOS_STS_RD_RESETVAL          (0x00000000U)
#define CSL_PCIEPHYRX_OBSERVE_REG1_LOS_STS_RD_MAX               (0x00000001U)

#define CSL_PCIEPHYRX_OBSERVE_REG1_CDR_FREQOFFSET_RD_MASK       (0x0003FF80U)
#define CSL_PCIEPHYRX_OBSERVE_REG1_CDR_FREQOFFSET_RD_SHIFT      (7U)
#define CSL_PCIEPHYRX_OBSERVE_REG1_CDR_FREQOFFSET_RD_RESETVAL   (0x00000000U)
#define CSL_PCIEPHYRX_OBSERVE_REG1_CDR_FREQOFFSET_RD_MAX        (0x000007ffU)

#define CSL_PCIEPHYRX_OBSERVE_REG1_LSDATAOUT_RD_MASK            (0x00000040U)
#define CSL_PCIEPHYRX_OBSERVE_REG1_LSDATAOUT_RD_SHIFT           (6U)
#define CSL_PCIEPHYRX_OBSERVE_REG1_LSDATAOUT_RD_RESETVAL        (0x00000000U)
#define CSL_PCIEPHYRX_OBSERVE_REG1_LSDATAOUT_RD_MAX             (0x00000001U)

#define CSL_PCIEPHYRX_OBSERVE_REG1_SPAREBITS_GANGARX_OBSERVE_REG1_MASK  (0x0000003FU)
#define CSL_PCIEPHYRX_OBSERVE_REG1_SPAREBITS_GANGARX_OBSERVE_REG1_SHIFT  (0U)
#define CSL_PCIEPHYRX_OBSERVE_REG1_SPAREBITS_GANGARX_OBSERVE_REG1_RESETVAL  (0x00000000U)
#define CSL_PCIEPHYRX_OBSERVE_REG1_SPAREBITS_GANGARX_OBSERVE_REG1_MAX  (0x0000003fU)

#define CSL_PCIEPHYRX_OBSERVE_REG1_RESETVAL                     (0x00000000U)

/* OBSERVE_REG2 */

#define CSL_PCIEPHYRX_OBSERVE_REG2_BERT_COUNT_RD_MASK           (0xFFF00000U)
#define CSL_PCIEPHYRX_OBSERVE_REG2_BERT_COUNT_RD_SHIFT          (20U)
#define CSL_PCIEPHYRX_OBSERVE_REG2_BERT_COUNT_RD_RESETVAL       (0x00000000U)
#define CSL_PCIEPHYRX_OBSERVE_REG2_BERT_COUNT_RD_MAX            (0x00000fffU)

#define CSL_PCIEPHYRX_OBSERVE_REG2_BERT_CAL_COUNT_RD_MASK       (0x000FFF00U)
#define CSL_PCIEPHYRX_OBSERVE_REG2_BERT_CAL_COUNT_RD_SHIFT      (8U)
#define CSL_PCIEPHYRX_OBSERVE_REG2_BERT_CAL_COUNT_RD_RESETVAL   (0x00000000U)
#define CSL_PCIEPHYRX_OBSERVE_REG2_BERT_CAL_COUNT_RD_MAX        (0x00000fffU)

#define CSL_PCIEPHYRX_OBSERVE_REG2_RXA_BSRXP_RD_MASK            (0x00000080U)
#define CSL_PCIEPHYRX_OBSERVE_REG2_RXA_BSRXP_RD_SHIFT           (7U)
#define CSL_PCIEPHYRX_OBSERVE_REG2_RXA_BSRXP_RD_RESETVAL        (0x00000000U)
#define CSL_PCIEPHYRX_OBSERVE_REG2_RXA_BSRXP_RD_MAX             (0x00000001U)

#define CSL_PCIEPHYRX_OBSERVE_REG2_RXA_BSRXN_RD_MASK            (0x00000040U)
#define CSL_PCIEPHYRX_OBSERVE_REG2_RXA_BSRXN_RD_SHIFT           (6U)
#define CSL_PCIEPHYRX_OBSERVE_REG2_RXA_BSRXN_RD_RESETVAL        (0x00000000U)
#define CSL_PCIEPHYRX_OBSERVE_REG2_RXA_BSRXN_RD_MAX             (0x00000001U)

#define CSL_PCIEPHYRX_OBSERVE_REG2_SPAREBITS_GANGARX_OBSERVE_REG2_MASK  (0x0000003FU)
#define CSL_PCIEPHYRX_OBSERVE_REG2_SPAREBITS_GANGARX_OBSERVE_REG2_SHIFT  (0U)
#define CSL_PCIEPHYRX_OBSERVE_REG2_SPAREBITS_GANGARX_OBSERVE_REG2_RESETVAL  (0x00000000U)
#define CSL_PCIEPHYRX_OBSERVE_REG2_SPAREBITS_GANGARX_OBSERVE_REG2_MAX  (0x0000003fU)

#define CSL_PCIEPHYRX_OBSERVE_REG2_RESETVAL                     (0x00000000U)

/* OBSERVE_REG3 */

#define CSL_PCIEPHYRX_OBSERVE_REG3_DCC_LOCK_RD_MASK             (0x80000000U)
#define CSL_PCIEPHYRX_OBSERVE_REG3_DCC_LOCK_RD_SHIFT            (31U)
#define CSL_PCIEPHYRX_OBSERVE_REG3_DCC_LOCK_RD_RESETVAL         (0x00000000U)
#define CSL_PCIEPHYRX_OBSERVE_REG3_DCC_LOCK_RD_MAX              (0x00000001U)

#define CSL_PCIEPHYRX_OBSERVE_REG3_DLL_LOCK_RD_MASK             (0x40000000U)
#define CSL_PCIEPHYRX_OBSERVE_REG3_DLL_LOCK_RD_SHIFT            (30U)
#define CSL_PCIEPHYRX_OBSERVE_REG3_DLL_LOCK_RD_RESETVAL         (0x00000000U)
#define CSL_PCIEPHYRX_OBSERVE_REG3_DLL_LOCK_RD_MAX              (0x00000001U)

#define CSL_PCIEPHYRX_OBSERVE_REG3_DLL_CALFB_RD_MASK            (0x20000000U)
#define CSL_PCIEPHYRX_OBSERVE_REG3_DLL_CALFB_RD_SHIFT           (29U)
#define CSL_PCIEPHYRX_OBSERVE_REG3_DLL_CALFB_RD_RESETVAL        (0x00000000U)
#define CSL_PCIEPHYRX_OBSERVE_REG3_DLL_CALFB_RD_MAX             (0x00000001U)

#define CSL_PCIEPHYRX_OBSERVE_REG3_RXA_OBS_RD_MASK              (0x1FFFFFE0U)
#define CSL_PCIEPHYRX_OBSERVE_REG3_RXA_OBS_RD_SHIFT             (5U)
#define CSL_PCIEPHYRX_OBSERVE_REG3_RXA_OBS_RD_RESETVAL          (0x00000000U)
#define CSL_PCIEPHYRX_OBSERVE_REG3_RXA_OBS_RD_MAX               (0x00ffffffU)

#define CSL_PCIEPHYRX_OBSERVE_REG3_SPAREBITS_GANGARX_OBSERVE_REG3_MASK  (0x0000001FU)
#define CSL_PCIEPHYRX_OBSERVE_REG3_SPAREBITS_GANGARX_OBSERVE_REG3_SHIFT  (0U)
#define CSL_PCIEPHYRX_OBSERVE_REG3_SPAREBITS_GANGARX_OBSERVE_REG3_RESETVAL  (0x00000000U)
#define CSL_PCIEPHYRX_OBSERVE_REG3_SPAREBITS_GANGARX_OBSERVE_REG3_MAX  (0x0000001fU)

#define CSL_PCIEPHYRX_OBSERVE_REG3_RESETVAL                     (0x00000000U)

/* DFT_OBSERVE_REG4 */

#define CSL_PCIEPHYRX_DFT_OBSERVE_REG4_BGTRIM_RD_MASK           (0xFFFF0000U)
#define CSL_PCIEPHYRX_DFT_OBSERVE_REG4_BGTRIM_RD_SHIFT          (16U)
#define CSL_PCIEPHYRX_DFT_OBSERVE_REG4_BGTRIM_RD_RESETVAL       (0x00000000U)
#define CSL_PCIEPHYRX_DFT_OBSERVE_REG4_BGTRIM_RD_MAX            (0x0000ffffU)

#define CSL_PCIEPHYRX_DFT_OBSERVE_REG4_RXTRIM_RD_MASK           (0x0000F800U)
#define CSL_PCIEPHYRX_DFT_OBSERVE_REG4_RXTRIM_RD_SHIFT          (11U)
#define CSL_PCIEPHYRX_DFT_OBSERVE_REG4_RXTRIM_RD_RESETVAL       (0x00000000U)
#define CSL_PCIEPHYRX_DFT_OBSERVE_REG4_RXTRIM_RD_MAX            (0x0000001fU)

#define CSL_PCIEPHYRX_DFT_OBSERVE_REG4_LOSTRIM_RD_MASK          (0x00000780U)
#define CSL_PCIEPHYRX_DFT_OBSERVE_REG4_LOSTRIM_RD_SHIFT         (7U)
#define CSL_PCIEPHYRX_DFT_OBSERVE_REG4_LOSTRIM_RD_RESETVAL      (0x00000000U)
#define CSL_PCIEPHYRX_DFT_OBSERVE_REG4_LOSTRIM_RD_MAX           (0x0000000fU)

#define CSL_PCIEPHYRX_DFT_OBSERVE_REG4_HS_RATE_RD_MASK          (0x00000060U)
#define CSL_PCIEPHYRX_DFT_OBSERVE_REG4_HS_RATE_RD_SHIFT         (5U)
#define CSL_PCIEPHYRX_DFT_OBSERVE_REG4_HS_RATE_RD_RESETVAL      (0x00000000U)
#define CSL_PCIEPHYRX_DFT_OBSERVE_REG4_HS_RATE_RD_MAX           (0x00000003U)

#define CSL_PCIEPHYRX_DFT_OBSERVE_REG4_PWM_RATE_RD_MASK         (0x0000001EU)
#define CSL_PCIEPHYRX_DFT_OBSERVE_REG4_PWM_RATE_RD_SHIFT        (1U)
#define CSL_PCIEPHYRX_DFT_OBSERVE_REG4_PWM_RATE_RD_RESETVAL     (0x00000000U)
#define CSL_PCIEPHYRX_DFT_OBSERVE_REG4_PWM_RATE_RD_MAX          (0x0000000fU)

#define CSL_PCIEPHYRX_DFT_OBSERVE_REG4_SPAREBITS_GANGARX_DFT_OBSERVE_REG4_MASK  (0x00000001U)
#define CSL_PCIEPHYRX_DFT_OBSERVE_REG4_SPAREBITS_GANGARX_DFT_OBSERVE_REG4_SHIFT  (0U)
#define CSL_PCIEPHYRX_DFT_OBSERVE_REG4_SPAREBITS_GANGARX_DFT_OBSERVE_REG4_RESETVAL  (0x00000000U)
#define CSL_PCIEPHYRX_DFT_OBSERVE_REG4_SPAREBITS_GANGARX_DFT_OBSERVE_REG4_MAX  (0x00000001U)

#define CSL_PCIEPHYRX_DFT_OBSERVE_REG4_RESETVAL                 (0x00000000U)

/* DFT_OBSERVE_REG5 */

#define CSL_PCIEPHYRX_DFT_OBSERVE_REG5_EN_RXA_RD_MASK           (0x80000000U)
#define CSL_PCIEPHYRX_DFT_OBSERVE_REG5_EN_RXA_RD_SHIFT          (31U)
#define CSL_PCIEPHYRX_DFT_OBSERVE_REG5_EN_RXA_RD_RESETVAL       (0x00000000U)
#define CSL_PCIEPHYRX_DFT_OBSERVE_REG5_EN_RXA_RD_MAX            (0x00000001U)

#define CSL_PCIEPHYRX_DFT_OBSERVE_REG5_EN_BG_RD_MASK            (0x40000000U)
#define CSL_PCIEPHYRX_DFT_OBSERVE_REG5_EN_BG_RD_SHIFT           (30U)
#define CSL_PCIEPHYRX_DFT_OBSERVE_REG5_EN_BG_RD_RESETVAL        (0x00000000U)
#define CSL_PCIEPHYRX_DFT_OBSERVE_REG5_EN_BG_RD_MAX             (0x00000001U)

#define CSL_PCIEPHYRX_DFT_OBSERVE_REG5_EN_DCC_RD_MASK           (0x20000000U)
#define CSL_PCIEPHYRX_DFT_OBSERVE_REG5_EN_DCC_RD_SHIFT          (29U)
#define CSL_PCIEPHYRX_DFT_OBSERVE_REG5_EN_DCC_RD_RESETVAL       (0x00000000U)
#define CSL_PCIEPHYRX_DFT_OBSERVE_REG5_EN_DCC_RD_MAX            (0x00000001U)

#define CSL_PCIEPHYRX_DFT_OBSERVE_REG5_EN_DLL_RD_MASK           (0x10000000U)
#define CSL_PCIEPHYRX_DFT_OBSERVE_REG5_EN_DLL_RD_SHIFT          (28U)
#define CSL_PCIEPHYRX_DFT_OBSERVE_REG5_EN_DLL_RD_RESETVAL       (0x00000000U)
#define CSL_PCIEPHYRX_DFT_OBSERVE_REG5_EN_DLL_RD_MAX            (0x00000001U)

#define CSL_PCIEPHYRX_DFT_OBSERVE_REG5_EN_EQ_ANA_RD_MASK        (0x08000000U)
#define CSL_PCIEPHYRX_DFT_OBSERVE_REG5_EN_EQ_ANA_RD_SHIFT       (27U)
#define CSL_PCIEPHYRX_DFT_OBSERVE_REG5_EN_EQ_ANA_RD_RESETVAL    (0x00000000U)
#define CSL_PCIEPHYRX_DFT_OBSERVE_REG5_EN_EQ_ANA_RD_MAX         (0x00000001U)

#define CSL_PCIEPHYRX_DFT_OBSERVE_REG5_EN_LOSD_RD_MASK          (0x04000000U)
#define CSL_PCIEPHYRX_DFT_OBSERVE_REG5_EN_LOSD_RD_SHIFT         (26U)
#define CSL_PCIEPHYRX_DFT_OBSERVE_REG5_EN_LOSD_RD_RESETVAL      (0x00000000U)
#define CSL_PCIEPHYRX_DFT_OBSERVE_REG5_EN_LOSD_RD_MAX           (0x00000001U)

#define CSL_PCIEPHYRX_DFT_OBSERVE_REG5_EN_COARSE1CAL_RD_MASK    (0x02000000U)
#define CSL_PCIEPHYRX_DFT_OBSERVE_REG5_EN_COARSE1CAL_RD_SHIFT   (25U)
#define CSL_PCIEPHYRX_DFT_OBSERVE_REG5_EN_COARSE1CAL_RD_RESETVAL  (0x00000000U)
#define CSL_PCIEPHYRX_DFT_OBSERVE_REG5_EN_COARSE1CAL_RD_MAX     (0x00000001U)

#define CSL_PCIEPHYRX_DFT_OBSERVE_REG5_EN_COARSE2CAL_RD_MASK    (0x01000000U)
#define CSL_PCIEPHYRX_DFT_OBSERVE_REG5_EN_COARSE2CAL_RD_SHIFT   (24U)
#define CSL_PCIEPHYRX_DFT_OBSERVE_REG5_EN_COARSE2CAL_RD_RESETVAL  (0x00000000U)
#define CSL_PCIEPHYRX_DFT_OBSERVE_REG5_EN_COARSE2CAL_RD_MAX     (0x00000001U)

#define CSL_PCIEPHYRX_DFT_OBSERVE_REG5_EN_OFFSETCAL_RD_MASK     (0x00800000U)
#define CSL_PCIEPHYRX_DFT_OBSERVE_REG5_EN_OFFSETCAL_RD_SHIFT    (23U)
#define CSL_PCIEPHYRX_DFT_OBSERVE_REG5_EN_OFFSETCAL_RD_RESETVAL  (0x00000000U)
#define CSL_PCIEPHYRX_DFT_OBSERVE_REG5_EN_OFFSETCAL_RD_MAX      (0x00000001U)

#define CSL_PCIEPHYRX_DFT_OBSERVE_REG5_EN_PHINT_RD_MASK         (0x00400000U)
#define CSL_PCIEPHYRX_DFT_OBSERVE_REG5_EN_PHINT_RD_SHIFT        (22U)
#define CSL_PCIEPHYRX_DFT_OBSERVE_REG5_EN_PHINT_RD_RESETVAL     (0x00000000U)
#define CSL_PCIEPHYRX_DFT_OBSERVE_REG5_EN_PHINT_RD_MAX          (0x00000001U)

#define CSL_PCIEPHYRX_DFT_OBSERVE_REG5_EN_PWM_RD_MASK           (0x00200000U)
#define CSL_PCIEPHYRX_DFT_OBSERVE_REG5_EN_PWM_RD_SHIFT          (21U)
#define CSL_PCIEPHYRX_DFT_OBSERVE_REG5_EN_PWM_RD_RESETVAL       (0x00000000U)
#define CSL_PCIEPHYRX_DFT_OBSERVE_REG5_EN_PWM_RD_MAX            (0x00000001U)

#define CSL_PCIEPHYRX_DFT_OBSERVE_REG5_EN_SYS_RD_MASK           (0x00100000U)
#define CSL_PCIEPHYRX_DFT_OBSERVE_REG5_EN_SYS_RD_SHIFT          (20U)
#define CSL_PCIEPHYRX_DFT_OBSERVE_REG5_EN_SYS_RD_RESETVAL       (0x00000000U)
#define CSL_PCIEPHYRX_DFT_OBSERVE_REG5_EN_SYS_RD_MAX            (0x00000001U)

#define CSL_PCIEPHYRX_DFT_OBSERVE_REG5_EN_DLLTRIM_RD_MASK       (0x00080000U)
#define CSL_PCIEPHYRX_DFT_OBSERVE_REG5_EN_DLLTRIM_RD_SHIFT      (19U)
#define CSL_PCIEPHYRX_DFT_OBSERVE_REG5_EN_DLLTRIM_RD_RESETVAL   (0x00000000U)
#define CSL_PCIEPHYRX_DFT_OBSERVE_REG5_EN_DLLTRIM_RD_MAX        (0x00000001U)

#define CSL_PCIEPHYRX_DFT_OBSERVE_REG5_EN_RXALDO_RD_MASK        (0x00040000U)
#define CSL_PCIEPHYRX_DFT_OBSERVE_REG5_EN_RXALDO_RD_SHIFT       (18U)
#define CSL_PCIEPHYRX_DFT_OBSERVE_REG5_EN_RXALDO_RD_RESETVAL    (0x00000000U)
#define CSL_PCIEPHYRX_DFT_OBSERVE_REG5_EN_RXALDO_RD_MAX         (0x00000001U)

#define CSL_PCIEPHYRX_DFT_OBSERVE_REG5_EN_RXDLDO_RD_MASK        (0x00020000U)
#define CSL_PCIEPHYRX_DFT_OBSERVE_REG5_EN_RXDLDO_RD_SHIFT       (17U)
#define CSL_PCIEPHYRX_DFT_OBSERVE_REG5_EN_RXDLDO_RD_RESETVAL    (0x00000000U)
#define CSL_PCIEPHYRX_DFT_OBSERVE_REG5_EN_RXDLDO_RD_MAX         (0x00000001U)

#define CSL_PCIEPHYRX_DFT_OBSERVE_REG5_EN_RXTERM_RD_MASK        (0x00010000U)
#define CSL_PCIEPHYRX_DFT_OBSERVE_REG5_EN_RXTERM_RD_SHIFT       (16U)
#define CSL_PCIEPHYRX_DFT_OBSERVE_REG5_EN_RXTERM_RD_RESETVAL    (0x00000000U)
#define CSL_PCIEPHYRX_DFT_OBSERVE_REG5_EN_RXTERM_RD_MAX         (0x00000001U)

#define CSL_PCIEPHYRX_DFT_OBSERVE_REG5_EN_PREDLL_RD_MASK        (0x00008000U)
#define CSL_PCIEPHYRX_DFT_OBSERVE_REG5_EN_PREDLL_RD_SHIFT       (15U)
#define CSL_PCIEPHYRX_DFT_OBSERVE_REG5_EN_PREDLL_RD_RESETVAL    (0x00000000U)
#define CSL_PCIEPHYRX_DFT_OBSERVE_REG5_EN_PREDLL_RD_MAX         (0x00000001U)

#define CSL_PCIEPHYRX_DFT_OBSERVE_REG5_RXALDO_STBL_IN_RD_MASK   (0x00004000U)
#define CSL_PCIEPHYRX_DFT_OBSERVE_REG5_RXALDO_STBL_IN_RD_SHIFT  (14U)
#define CSL_PCIEPHYRX_DFT_OBSERVE_REG5_RXALDO_STBL_IN_RD_RESETVAL  (0x00000000U)
#define CSL_PCIEPHYRX_DFT_OBSERVE_REG5_RXALDO_STBL_IN_RD_MAX    (0x00000001U)

#define CSL_PCIEPHYRX_DFT_OBSERVE_REG5_RXDLDO_STBL_IN_RD_MASK   (0x00002000U)
#define CSL_PCIEPHYRX_DFT_OBSERVE_REG5_RXDLDO_STBL_IN_RD_SHIFT  (13U)
#define CSL_PCIEPHYRX_DFT_OBSERVE_REG5_RXDLDO_STBL_IN_RD_RESETVAL  (0x00000000U)
#define CSL_PCIEPHYRX_DFT_OBSERVE_REG5_RXDLDO_STBL_IN_RD_MAX    (0x00000001U)

#define CSL_PCIEPHYRX_DFT_OBSERVE_REG5_EN_RXD_RD_MASK           (0x00001000U)
#define CSL_PCIEPHYRX_DFT_OBSERVE_REG5_EN_RXD_RD_SHIFT          (12U)
#define CSL_PCIEPHYRX_DFT_OBSERVE_REG5_EN_RXD_RD_RESETVAL       (0x00000000U)
#define CSL_PCIEPHYRX_DFT_OBSERVE_REG5_EN_RXD_RD_MAX            (0x00000001U)

#define CSL_PCIEPHYRX_DFT_OBSERVE_REG5_INV_RXPN_PAIR_RD_MASK    (0x00000800U)
#define CSL_PCIEPHYRX_DFT_OBSERVE_REG5_INV_RXPN_PAIR_RD_SHIFT   (11U)
#define CSL_PCIEPHYRX_DFT_OBSERVE_REG5_INV_RXPN_PAIR_RD_RESETVAL  (0x00000000U)
#define CSL_PCIEPHYRX_DFT_OBSERVE_REG5_INV_RXPN_PAIR_RD_MAX     (0x00000001U)

#define CSL_PCIEPHYRX_DFT_OBSERVE_REG5_EN_SAOC_DIG_RD_MASK      (0x00000400U)
#define CSL_PCIEPHYRX_DFT_OBSERVE_REG5_EN_SAOC_DIG_RD_SHIFT     (10U)
#define CSL_PCIEPHYRX_DFT_OBSERVE_REG5_EN_SAOC_DIG_RD_RESETVAL  (0x00000000U)
#define CSL_PCIEPHYRX_DFT_OBSERVE_REG5_EN_SAOC_DIG_RD_MAX       (0x00000001U)

#define CSL_PCIEPHYRX_DFT_OBSERVE_REG5_EN_EQ_DIG_RD_MASK        (0x00000200U)
#define CSL_PCIEPHYRX_DFT_OBSERVE_REG5_EN_EQ_DIG_RD_SHIFT       (9U)
#define CSL_PCIEPHYRX_DFT_OBSERVE_REG5_EN_EQ_DIG_RD_RESETVAL    (0x00000000U)
#define CSL_PCIEPHYRX_DFT_OBSERVE_REG5_EN_EQ_DIG_RD_MAX         (0x00000001U)

#define CSL_PCIEPHYRX_DFT_OBSERVE_REG5_LOS_TO_CDR_VAL_RD_MASK   (0x00000100U)
#define CSL_PCIEPHYRX_DFT_OBSERVE_REG5_LOS_TO_CDR_VAL_RD_SHIFT  (8U)
#define CSL_PCIEPHYRX_DFT_OBSERVE_REG5_LOS_TO_CDR_VAL_RD_RESETVAL  (0x00000000U)
#define CSL_PCIEPHYRX_DFT_OBSERVE_REG5_LOS_TO_CDR_VAL_RD_MAX    (0x00000001U)

#define CSL_PCIEPHYRX_DFT_OBSERVE_REG5_SPAREBITS_GANGARX_DFT_OBSERVE_REG5_MASK  (0x000000FFU)
#define CSL_PCIEPHYRX_DFT_OBSERVE_REG5_SPAREBITS_GANGARX_DFT_OBSERVE_REG5_SHIFT  (0U)
#define CSL_PCIEPHYRX_DFT_OBSERVE_REG5_SPAREBITS_GANGARX_DFT_OBSERVE_REG5_RESETVAL  (0x00000000U)
#define CSL_PCIEPHYRX_DFT_OBSERVE_REG5_SPAREBITS_GANGARX_DFT_OBSERVE_REG5_MAX  (0x000000ffU)

#define CSL_PCIEPHYRX_DFT_OBSERVE_REG5_RESETVAL                 (0x00000000U)

/* DLLOFFSET_TRIM_REG */

#define CSL_PCIEPHYRX_DLLOFFSET_TRIM_REG_MEM_DLLOFFSETTRIM_MASK  (0xFC000000U)
#define CSL_PCIEPHYRX_DLLOFFSET_TRIM_REG_MEM_DLLOFFSETTRIM_SHIFT  (26U)
#define CSL_PCIEPHYRX_DLLOFFSET_TRIM_REG_MEM_DLLOFFSETTRIM_RESETVAL  (0x00000000U)
#define CSL_PCIEPHYRX_DLLOFFSET_TRIM_REG_MEM_DLLOFFSETTRIM_MAX  (0x0000003fU)

#define CSL_PCIEPHYRX_DLLOFFSET_TRIM_REG_MEM_OVRD_EFUSE_DLLOFFSETTRIM_MASK  (0x02000000U)
#define CSL_PCIEPHYRX_DLLOFFSET_TRIM_REG_MEM_OVRD_EFUSE_DLLOFFSETTRIM_SHIFT  (25U)
#define CSL_PCIEPHYRX_DLLOFFSET_TRIM_REG_MEM_OVRD_EFUSE_DLLOFFSETTRIM_RESETVAL  (0x00000000U)
#define CSL_PCIEPHYRX_DLLOFFSET_TRIM_REG_MEM_OVRD_EFUSE_DLLOFFSETTRIM_MAX  (0x00000001U)

#define CSL_PCIEPHYRX_DLLOFFSET_TRIM_REG_MEM_SPAREBITS_GANGARX_DLLOFFSET_TRIM_REG_MASK  (0x01FFFFFFU)
#define CSL_PCIEPHYRX_DLLOFFSET_TRIM_REG_MEM_SPAREBITS_GANGARX_DLLOFFSET_TRIM_REG_SHIFT  (0U)
#define CSL_PCIEPHYRX_DLLOFFSET_TRIM_REG_MEM_SPAREBITS_GANGARX_DLLOFFSET_TRIM_REG_RESETVAL  (0x00000000U)
#define CSL_PCIEPHYRX_DLLOFFSET_TRIM_REG_MEM_SPAREBITS_GANGARX_DLLOFFSET_TRIM_REG_MAX  (0x01ffffffU)

#define CSL_PCIEPHYRX_DLLOFFSET_TRIM_REG_RESETVAL               (0x00000000U)

#ifdef __cplusplus
}
#endif
#endif
